Principal AMS Verification Engineer

Analog Devices•Wilmington, MA

2d•Onsite

About The Position

Analog Devices (ADI) is seeking a motivated Principal AMS Verification Engineer for the IC development of new products. These products are integrated high-speed and precision signal chains for Automated Test Equipment (ATE) applications, utilizing advanced internal BiCMOS SiGe processes and standard CMOS processes. The designs are combined into custom System-In-a-Package (SIP) solutions, also known as chiplets. The role involves system-level verification of digital and mixed-signal circuits, including high-speed drivers, receivers, DACs, SPI/JTAG/SerDes interfaces, calibration routines, and digital controls. This is a multi-die verification effort using Verilog and Spice simulators. A verification plan will be created at the product start, outlining verification methods and block model plans. The candidate will also work with evaluation engineers to compare simulation and lab results. The ideal candidate is self-motivated, a fast learner, and possesses strong technical, analytical, and communication skills. This position offers opportunities to gain system-level design experience, work with new internal BiCMOS processes, and collaborate with an experienced development team.

Requirements

BSEE, MSEE and 6+ years experience preferred
Strong Knowledge of System Verilog, UVM and OOP
Strong Knowledge of Verilog and Spice simulators
Knowledge of Analog circuits and CAD tools (Cadence Virtuoso).
Knowledge of scripting languages such as Python, TCL, Perl, Bash.
Ability to problem solve at the circuit and system level
Strong presentation and writing/communication skills.
Ability to collaborate in a team environment and across organizations

Responsibilities

Ownership of the system level verification plan and effort for multi-die advanced custom chiplet products
Develop test bench environments and directed functional, random, and constrained random tests.
Implement coverage driven verification methodologies.
Create functional coverage metrics.
Ensure these environments allow verification, design, product, and test engineers to efficiently develop functional test cases.
Define and develop block level modeling and verification strategies based on design requirements and architecture
Specify, and perform as necessary, block and chip level RTL, gate, and mixed signal co-simulation regressions.
Track progress against verification plan
Work with designers and product/apps engineers to achieve functional coverage goals and to debug the design and environment
Work closely with evaluation engineers when silicon arrives to compare and contrast simulation results
Preparation and presentation of verification plan and final review documentation packages