Principal Test Engineer

Microsoft • Hillsboro, OR

5d

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops and operates infrastructure and foundational technologies for Microsoft’s online businesses and Azure platform. The Compute Silicon & Manufacturing Engineering organization designs, develops, manufactures, and packages Microsoft computer chips, including Azure Cobalt. The Silicon Manufacturing and Product Engineering team supports hardware manufacturing by improving planning, quality, delivery, scale, and sustainability.

The Principal Test Engineer will support new product development and manufacturing, with a primary focus on scan (structural) test. The role contributes to silicon bring-up, validation, and manufacturing readiness, working with cross-functional partners across semiconductor fabrication, manufacturing test, and packaging. It includes ATE test-program development and support for scan patterns, test methods, bring-up, characterization, debug, and yield analysis. The engineer applies DFT knowledge and industry-standard scan testing methods, executes defined test plans, identifies and escalates risks using technical data, and collaborates to achieve scan-test readiness, coverage closure, and issue resolution. Projects may involve high-performance computing, AI, GPUs, or telecom.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or a master's degree in one of these fields and 6+ years; or a bachelor's degree in one of these fields and 8+ years; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Ability to provide proof of citizenship, U.S. residency, or other protected status for assessment of eligibility to access export-controlled information; citizenship is verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.
• Working knowledge of DFT, including scan architecture, ATPG, fault models, silicon fabrication processes, product qualification and reliability, and basic transistor theory.
• Knowledge of industry-standard DFT features, including scan (SAF/TDF), JTAG, boundary scan, and at-speed testing.
• Understanding of scan fault models such as stuck-at and transition faults, coverage targets, and defect-screening methodologies.

Nice To Haves

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 5+ years of technical engineering experience; or a master's degree in one of these fields and 8+ years; or a bachelor's degree in one of these fields and 12+ years; or equivalent experience.
• At least 1 year of experience working on or leading projects from beginning to end.
• At least 5 years of experience in integrated circuit development, including pre-silicon, first-silicon bring-up, or new product introduction.
• At least 5 years of product and test engineering experience, with hands-on exposure to ATE test-program development, bring-up, and scan debug.
• Experience with complex SoCs or chips, including high-performance, AI, or advanced-node designs.
• Clear written and verbal communication skills and ability to present technical data effectively.
• Experience collaborating with cross-functional teams in a structured development environment.
• Working knowledge of probability, statistics, and basic DOE concepts.
• Familiarity with DFT and DFM techniques, especially scan/structural test methodologies.
• Experience with scan/ATPG methodologies, including pattern generation, validation, and test flows.
• Understanding of silicon bring-up, debug, and characterization on ATE platforms such as Advantest 93K for scan-test content.
• Exposure to mixed-signal IP test development and its interaction with structural test.
• Basic device physics background.
• Adaptability, curiosity, and a constructive problem-solving approach; a growth mindset and desire to expand technical depth.
• Fundamentals of computer architecture.
• Good unit and integration testing skills.
• Proficiency with Linux-based environments.
• Experience debugging and optimizing test programs, ATPG patterns, or validation flows.
• Customer-focused mindset with attention to quality, coverage, and execution.
• Ability to deliver results on assigned tasks with guidance and sound technical judgment in scoping and resolving well-defined problems.

Responsibilities

• Support product and engineering activities for new product development and manufacturing, primarily focused on scan (structural) test.
• Contribute to silicon bring-up, validation, and manufacturing readiness with cross-functional partners.
• Support semiconductor IC development across fabrication, manufacturing test, and packaging phases.
• Contribute to ATE test-program development, including scan-pattern integration, test-method implementation, bring-up, silicon characterization, debug, and yield analysis for logic defects.
• Execute defined test plans and methodologies, identify issues, and escalate risks with clear technical data.
• Collaborate with design, DFT, product, and manufacturing teams on scan-test readiness, coverage closure, and issue resolution.
• Support scan-test content generation, including ATPG pattern validation, pattern bring-up, and post-silicon debug.
• Use scan diagnosis tools for failure analysis, defect localization, and yield-improvement activities.
• Work with DFT teams on simulation, emulation, and pattern verification for scan-test validation.

Benefits

• Certain roles may be eligible for benefits and other compensation; additional benefits and pay information is available through the linked Microsoft careers page.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal