Principal Test Engineer

Microsoft•Redmond, WA

5d•$142,800 - $304,200

About The Position

Microsoft Silicon, Cloud, Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft’s cloud infrastructure and supports the company’s online businesses and Azure platform. Within SCHIE, the Compute Silicon & Manufacturing Engineering organization designs, develops, manufactures, and packages computer chips, including Azure Cobalt. The Silicon Manufacturing and Product Engineering team helps define and deliver operational success for hardware manufacturing, improving planning, quality, delivery, scale, and sustainability. The Principal Test Engineer supports product and engineering activities for new product development and manufacturing, with a primary focus on scan (structural) test. The role contributes to silicon bring-up, validation, and manufacturing readiness, and supports semiconductor IC development through fabrication, manufacturing test, and packaging. It involves ATE test program development and execution, scan pattern integration and validation, test bring-up, silicon characterization, debug, and yield analysis. The engineer collaborates with design, DFT, product, and manufacturing teams to support test readiness, coverage closure, and issue resolution, while applying scan diagnosis and other DFT methods to analyze failures and improve yield. The position requires a relevant engineering or computer science degree with experience, or equivalent experience. The role also requires passing Microsoft’s Cloud Background Check and verification of eligibility to access export-controlled information. The stated U.S. base pay range is $142,800–$274,800 per year, with a different range of $188,000–$304,200 for the San Francisco Bay Area and New York City metropolitan area. Certain roles may be eligible for benefits and other compensation; further details are provided through Microsoft’s careers pay information page.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or a master’s degree in one of these fields and 6+ years; or a bachelor’s degree in one of these fields and 8+ years; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Must provide proof of citizenship, U.S. residency, or other protected status to assess eligibility for export-controlled information access; citizenship is verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.
Working knowledge of Design-for-Test (DFT), including scan architecture, ATPG, fault models, silicon fabrication processes, product qualification and reliability, and basic transistor theory.

Nice To Haves

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 5+ years of technical engineering experience; or a master’s degree in one of these fields and 8+ years; or a bachelor’s degree in one of these fields and 12+ years; or equivalent experience.
At least 1 year of experience working on or leading projects from beginning to end.
At least 5 years of experience in integrated circuit development, including pre-silicon, first silicon bring-up, or new product introduction.
At least 5 years of product and test engineering experience, with hands-on exposure to ATE test program development, bring-up, and scan debug.
Experience with complex SoCs or chips, including exposure to high-performance, AI, or advanced-node designs.
Clear written and verbal communication skills and ability to present technical data effectively.
Experience collaborating with cross-functional teams in a structured development environment.
Working knowledge of probability, statistics, and basic DOE concepts.
Familiarity with DFT and DFM techniques, especially scan and structural test methodologies.
Experience with scan/ATPG methodologies, including pattern generation, validation, and test flows.
Understanding of silicon bring-up, debug, and characterization on ATE platforms, such as Advantest 93K, for scan test content.
Exposure to mixed-signal IP test development and its interaction with structural test.
Basic device physics background.
Adaptability, curiosity, and a constructive problem-solving approach.
Growth mindset and desire to learn and expand technical depth.
Fundamentals of computer architecture.
Good unit and integration testing skills.
Proficiency with Linux-based environments.
Experience debugging and optimizing test programs, ATPG patterns, or validation flows.
Customer-focused mindset with attention to quality, coverage, and execution.
Ability to deliver results on assigned tasks with guidance.
Sound technical judgment in scoping and resolving well-defined problems.

Responsibilities

Support product and engineering activities for new product development and manufacturing, primarily focused on scan (structural) test.
Contribute to silicon bring-up, validation, and manufacturing readiness in collaboration with cross-functional partners.
Support semiconductor IC development across fabrication, manufacturing test, and packaging phases.
Contribute to ATE test program development, including scan pattern integration, test method implementation, bring-up, silicon characterization, debug, and yield analysis for logic defects.
Execute defined test plans and methodologies, identify issues, and escalate risks with clear technical data.
Collaborate with design, DFT, product, and manufacturing teams to support scan test readiness, coverage closure, and issue resolution.
Apply industry-standard DFT features, including scan (SAF/TDF), JTAG, boundary scan, and at-speed testing.
Support scan test content generation, including ATPG pattern validation, pattern bring-up, and post-silicon debug.
Use scan diagnosis tools to perform failure analysis, identify defect locations, and support yield improvement.
Work with DFT teams on simulation, emulation, and pattern verification for scan test validation.
Gain exposure to product areas such as high-performance computing, AI, GPUs, and telecom as applicable to assigned projects.