Principal Test Development Engineer

Marvell Technology • Santa Clara, CA

6d

About The Position

As a test development principal engineer in Marvell’s Operations business group, you will test features on semiconductor chips for internal and external customers and help ensure underperforming units are not shipped. You will work closely with design teams to ensure chip features are testable and results meet customer specifications. The role may involve writing code or developing new testing strategies when chip capabilities exceed current testing equipment.

You will develop test programs and tester hardware for high-speed testing on the Advantest 93K platform, create test plans and methodologies, and collaborate with DFT/DFM teams and product engineers to optimize test flow, improve yield, and release production test programs. The role calls for urgency, accountability, and the ability to manage multiple tasks in a fast-paced environment.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 5–10 years of related professional experience, or a master’s degree in those fields with 3–5 years of experience.
• At least 6 years of test program development experience on the Advantest 93K ATE tester platform.
• At least 4 years of experience in high-speed digital testing.
• Demonstrable experience in ATE testing, test methodology, silicon process, and DFT/DFM.
• Demonstrable experience with C/C++, Perl, Python, and Linux.
• Effective interpersonal, teamwork, and communication skills.
• Strong problem-solving, teamwork, collaboration, and interpersonal skills.
• Urgency and accountability, and the ability to multitask in a fast-paced environment.

Responsibilities

• Develop test programs on the Advantest 93K tester platform and design tester hardware for high-speed testing.
• Develop characterization, production, and wafer sort test programs on the Advantest 93K tester.
• Create detailed test plans and documentation of test methodologies to meet product specifications.
• Participate in testability reviews with DFT/DFM teams to define and enhance yield and test methodologies.
• Convert test patterns from the design simulation environment to ATE format.
• Lead test flow optimization, test time reduction, test insertion and removals, yield improvement, and release of production test programs with product engineers.
• Test semiconductor chip features for internal and external customers and help ensure results meet customer specifications.

Benefits

• Eligible to participate in bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Employee stock purchase plan with a 2-year look back.
• Family support programs.
• Mental health resources.
• Recognition and service awards.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal