Principal Technical Program Manager – FEIC ASIC Development – TeraWave

BLUE ORIGIN•San Diego, CA

16d•$249,235 - $348,929

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. Blue Origin is seeking a Technical Program Manager to lead development of the TeraWave Front-End Integrated Circuit (FEIC) chipset family. These chips, performing IF-to-RF conversion, low-noise and power-efficient mmwave amplification, and LO generation, form the core building blocks of TeraWave's mm-wave phased array implementation across both payloads and user terminals. They play a decisive role in overall link performance, defining the system's mm-wave noise figure, power efficiency, resiliency, and cost structure. This role owns the full product lifecycle—from architecture definition through tapeout and into production—including antenna co-development. As the key driving force behind the program, the TPM will orchestrate internal teams, external vendors, and IP providers to deliver against technical and schedule targets.

Requirements

Bachelor's degree in Electrical Engineering
10+ years in technical program management or RF/mixed-signal semiconductor development
5+ years managing RFIC or mixed-signal ASIC programs from specification through tapeout and silicon bring-up, including multi-variant or multi-process-node programs
Experience coordinating development across multiple design vendors and process technologies simultaneously, including vendor selection, SOW definition, and technical milestone management
Demonstrated expertise in technical risk identification and program planning for analog/RF systems

Nice To Haves

Advanced degree in Electrical Engineering with focus on RF, microwave, or mixed-signal IC design
Familiarity with millimeter-wave RFIC architectures including power amplifiers, LNAs, fractional-N PLLs, and mixer design at Ka/V/E-band frequencies
Experience with Antenna-in-Package (AiP) co-design and RFIC packaging for phased-array applications, including pin-map, substrate, and bump/ball pitch co-optimization
Knowledge of RF CMOS/SOI or BiCMOS process technologies and their design constraints
Background in satellite communications, phased-array antenna systems, or space-grade RFIC qualification

Responsibilities

Drive parallel development FEIC chipsets from architecture definition through tapeout, silicon bring-up and production on accelerated & interleaved schedules.
Build and maintain integrated schedules across multiple design services vendors and partners, tracking inter-variant dependencies and shared design elements.
Coordinate closure of architecture trades, frequency planning and digital control interface selection.
Track and mitigate risks related to vendor schedule and pricing divergences, antenna design strategy, band emission compliance, and cross-variant design reuse targets.
Align FEIC specifications and analog interface definitions to ensure system-level compatibility, including analog I/O pin-map and footprint co-design.
Manage antenna co-development, ensuring FEIC electrical specs are compatible with antenna integration and that end-product deliverable is aligned across stakeholders.
Monitor performance, power, and yield targets and drive DFT and final test strategy definition with vendors.
Coordinate multi-variant mask planning including metal-layer variants to minimize tapeout risk and cost across frequency and feature variants.
Oversee the post-silicon development phases including bring-up, bench-validation, characterization, qualification and production ramp.