Principal Signal and Power Integrity Engineer.

Delos Data Inc•Palo Alto, CA

6d•$180,000 - $240,000•Hybrid

About The Position

We are a stealth‑mode startup building foundational technology to address performance, scalability, and resiliency challenges in large‑scale AI data center clusters. We are backed by top‑tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on‑site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.

Requirements

B.S./M.S. in Electrical Engineering or related field.
Deep understanding of EM theory, transmission lines, and high‑speed signaling.
Expertise with SI/PI tools (Keysight ADS, Ansys HFSS, Cadence Sigrity/PowerSI).
Experience with UCIe, D2D, SerDes, or Ethernet interfaces.
Knowledge of PCB materials, stack‑ups, and constraint‑driven design.
Hands‑on experience with VNA, TDR, oscilloscopes.

Nice To Haves

Python/Matlab scripting for automation is a plus.

Responsibilities

Perform pre‑ and post‑layout SI simulations (eye diagrams, crosstalk, insertion/return loss) for UCIe, D2D, SerDes, and Ethernet links.
Model PDNs for low‑voltage, high‑current rails; run AC/DC, impedance, and IR‑drop simulations; come up with decoupling cap selection.
Build and validate S‑parameter, IBIS‑AMI, and behavioral models for packages, PCBs, sockets and cables.
Guide PCB/package layout teams on stack‑ups, routing constraints, return‑path continuity, and decoupling strategy.
Conduct bring‑up, VNA/TDR measurements, oscilloscope validation, and correlate hardware results with simulations.
Collaborate with IC design, packaging, and board teams to define electrical requirements and debug issues.
Evaluate new SI/PI methodologies, materials, and tools for next‑generation architectures.
Evaluate emerging interconnect technologies such as CPC, CPO, and establish electrical-optical-electrical end-to-end simulation and validation methodologies.