Principal RTL Design Engineer

SambaNova • San Jose, CA

2d • $180,000 - $255,000

About The Position

SambaNova Systems is seeking a Principal RTL Design Engineer to take ownership of the microarchitecture and RTL for a significant block or subsystem within their next-generation Reconfigurable Dataflow Unit (RDU). The RDU is the core silicon powering their AI workload acceleration systems. This senior individual contributor role involves end-to-end responsibility, from microarchitecture specification through RTL implementation, quality closure, and tape-out, with a strong emphasis on managing power, performance, and area (PPA) trade-offs. The role requires aggressive frequency target achievement through strategic pipelining and area optimization. Collaboration with architects, design verification, physical design, software, and compiler teams is essential for functional and timing convergence, as well as for prototyping features that enhance application-level performance. The successful candidate will play a key role in setting the technical standards for digital design within the team, influencing design reviews, adopted methodologies, and the evolution of the design flow.

Requirements

• BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design
• Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent
• High-frequency design experience: datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets
• Deep foundation in computer architecture and digital logic design: arbitration, flow control, clock domain crossing, and memory structures
• Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
• Physical-design awareness: converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team
• Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows
• Demonstrated technical leadership without formal authority: setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers
• Scripting in Python for design and flow automation

Nice To Haves

• Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem
• Industry-standard interconnects and protocols: AXI, PCIe, Ethernet, HBM/DDR
• AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures
• Formal property checking applied to design intent
• Advanced TSMC nodes and multi-die or chiplet design
• Performance modeling and analysis to support architectural trade-offs
• Fluency with Claude or other AI tools applied to RTL design and flow development
• MS or PhD in EE, CE, or CS with 10+ years of experience in ASIC RTL design

Responsibilities

• Own microarchitecture and RTL implementation for a major block or subsystem of the RDU, from specification through tape-out
• Define and document microarchitecture specifications for complex digital blocks in compute, memory, or on-chip network subsystems
• Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
• Hit aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
• Own PPA for your area: make and defend the power, performance, and area trade-offs using advanced techniques for high-speed design
• Drive timing closure with physical design: synthesis, STA, critical-path iteration, and response to floorplan and congestion feedback
• Own design quality gates for your area: lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
• Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures
• Work with architects and software teams to prototype and evaluate features that improve application-level performance
• Drive AI, automation, and new EDA tool methodologies into the design flow
• Set the technical bar in design reviews and mentor design engineers

Benefits

• Equity
• 95% premium coverage for employee medical insurance
• 77% premium coverage for dependents
• Health Savings Account (HSA) with employer contribution
• Dental insurance
• Vision insurance
• Short-term Disability insurance
• Long-term Disability insurance
• Basic Life insurance
• Voluntary Life insurance
• AD&D insurance
• Flexible Spending Account (FSA) options (Health Care, Limited Purpose, Dependent Care)
• Full subscription to Headspace
• Gympass+ membership with access to physical gyms
• One Medical membership
• Counseling services with an Employee Assistance Program

What This Job Offers

• Job Type: Full-time
• Career Level: Principal