Principal RFIC Design Engineer
About The Position
WD is seeking a Principal RFIC Design Engineer to join their team. This role involves the design of high-performance analog and mixed-signal circuit blocks. Responsibilities span the entire design cycle, including architecture, simulation, optimization, layout supervision, verification, test plan preparation, characterization, reliability assessment, modeling, simulation-to-bench correlation, bench evaluation, and documentation. The position requires strong communication skills to interact with various levels and cross-functional groups, a demonstrated track record of circuit innovation, teamwork, adaptability, and openness to constructive criticism.
Requirements
- Hands-on design and development experience in analog and mixed-signal integrated circuit.
- Experience in at least one preferably multiple area of full CMOS circuit design and development in: Amplifiers – operational, instrumentation, wide-bandwidth etc.; PMIC – Linear and switched regulators, Low-drop out regulators etc.; Data converters – ADC, DAC, Flash and SAR type.
- Experience in 40nm and below CMOS technology.
- Demonstrable track record of successful design releases and mass production.
- Thorough knowledge of industry standard EDA tools (Cadence, Mentor, Siemens, Ansys etc.).
- Experience with analog layout techniques of mismatch reduction, gradient suppression, parasitic effects minimization.
- Experience with floor planning, block level routing and top level chip routing.
- Knowledge of high performance and deep CMOS analog reliability considerations such as EM-IR, SOA and VDR and relevant mitigation techniques.
- Functional knowledge of logic digital circuits and understanding of basic digital design flow.
- Strong written and verbal communication skills.
- BSEE with minimum 10+ years of experience OR MSEE with minimum 8+ years of experience OR PhD with minimum 4+ years of experience.
Nice To Haves
- Experience working with distributed design teams.
Responsibilities
- Design of high performance analog and mixed-signal circuit blocks.
- Transistor level, block level and module level circuit architecture, design, simulation, optimization, layout supervision, layout verification.
- Preparation of test plan for the test group.
- Product characterization, reliability and yield assessment and modeling.
- Simulation to bench and bench to test correlation.
- Bench evaluation both at silicon level and at applications level.
- Documentation.
- Communicate at all levels and with cross functional groups.
Benefits
- Paid vacation time
- Paid sick leave
- Medical/dental/vision insurance
- Life, accident and disability insurance
- Tax-advantaged flexible spending and health savings accounts
- Employee assistance program
- Other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
- Tuition reimbursement
- Transit
- The Applause Program
- Employee stock purchase plan
- WD Savings 401(k) Plan
- Eligibility for bonuses under WD’s Short Term Incentive Plan (“STI Plan”) or the Sales Incentive Plan (“SIP”)
- Potential eligibility for annual Long-Term Incentive (LTI) program (restricted stock units (RSUs) or cash equivalents)
- RSU awards for eligible new hires
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What This Job Offers
Job Type
Full-time
Career Level
Principal
