Principal Physical Verification Engineer

Celero CommunicationsIrvine, CA

About The Position

Senior/Principal Full-Chip Physical Verification Engineer Key Responsibilities Team & Project Leadership Lead full chip Physical Verification effort Own execution plans, schedules for full-chip Drive accountability for quality, milestones, and tapeout readiness. Conduct full chip and blocks PV checks Physical Verification Ownership Ownership of full chip verification Work with internal analog team to ensure clean IP delivery Responsible for running and analyzing DRC/ERC/LUP/PERC results Experience with using either ICV or Calibre verification tools Understanding advance TSMC DRC rules Cross-Functional Collaboration Partner with analog, block, chip top owners to ensure clean floorplan Provide early guidance on corner case requirements Influence floorplan constraints, hierarchy, and implementation strategy Participate in tapeout readiness reviews

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering or related field.
  • 7+ years of experience with full-chip verifications
  • Proven hands-on experience with Physical Verification tool (ICV/Calibre)
  • Able to assemble a flow to support block/chip level PV
  • Strong expertise in Floorplanning to avoid DRC/LVS issues
  • Provide guidance to analog IP team to allow for clean integration
  • Understanding advance TSMC DRC rules

Nice To Haves

  • Experience in advanced technology nodes (7nm, 5nm, 3nm)
  • Automation skills using Tcl, Python, or shell scripting

Responsibilities

  • Lead full chip Physical Verification effort
  • Own execution plans, schedules for full-chip
  • Drive accountability for quality, milestones, and tapeout readiness.
  • Conduct full chip and blocks PV checks
  • Ownership of full chip verification
  • Work with internal analog team to ensure clean IP delivery
  • Responsible for running and analyzing DRC/ERC/LUP/PERC results
  • Partner with analog, block, chip top owners to ensure clean floorplan
  • Provide early guidance on corner case requirements
  • Influence floorplan constraints, hierarchy, and implementation strategy
  • Participate in tapeout readiness reviews
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