Senior Principal Verification Engineer

Renesas Electronics•Chandler, AZ

8d•Onsite

About The Position

Renesas is seeking an experienced Sr Principal Verification Engineer to lead the verification efforts for our Automotive PMIC (Power Management Integrated Circuit) product line. This role combines deep expertise in mixed-signal verification methodology with strong leadership capabilities to mentor junior engineers and drive verification strategy across multiple product platforms. The ideal candidate will have comprehensive knowledge of analog, digital, and mixed-signal verification techniques, combined with hands-on experience debugging complex automotive power management systems.

Requirements

MS or PhD in Electrical Engineering, Computer Engineering, or related field
15+ years of experience in mixed-signal or analog circuit verification
Deep understanding of all aspects of mixed-signal verification environment architecture and implementation
Hands-on experience with Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration
Proficiency in RTL and behavioral simulation tools (e.g., Spectre, Xcelium)
Strong understanding of Gate-Level Simulation (GLS) flows and ability to set up and debug GLS simulations
Proven expertise debugging both analog blocks (switched-mode regulators, LDO, bandgap, reference circuits) and digital RTL
Experience with automotive PMIC or power management IC design and verification
Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages
Solid understanding of verification methodologies: UVM, assertions, coverage-driven verification
Experience interfacing with multiple verification domains: functional, post-silicon, ATE test correlation
Excellent problem-solving and debugging skills with strong analytical mindset
Leadership and mentoring experience

Responsibilities

Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration for PMIC designs
Develop and implement comprehensive verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200)
Set up and optimize Gate-Level Simulation (GLS) flows, correlating with RTL simulation results to identify and resolve discrepancies
Lead debugging activities for complex analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces
Conduct in-depth RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners
Collaborate closely with cross-functional teams: Design, Application Engineering, ATE (Automatic Test Equipment), and Silicon Validation to ensure seamless verification handoffs
Mentor and lead junior verification engineers, defining best practices and establishing verification methodologies
Troubleshoot and debug complex design issues involving interactions between analog and digital domains using simulation and measurement techniques
Drive continuous improvement of verification tools, methodologies, and infrastructure, evaluating emerging verification technologies and AI-based solutions
Create and maintain comprehensive verification documentation, test plans, and coverage metrics