Principal Physical Design Engineer

Celero Communications • Irvine, CA

3d

About The Position

We are seeking a Senior/Principal Physical Design Engineer to own the physical implementation of System-on-Chips (SoCs) or complex digital blocks. This role involves managing floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance. You will be responsible for resolving timing, congestion, and EM/IR issues in collaboration with Frontend Designers, and for running Static Timing Analysis (STA) and physical verification. Additionally, you will fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations, and drive automation and improve flow robustness using scripting languages. This role requires cross-functional leadership, partnering with architects, logic designers, and the analog design team for tapeout readiness.

Requirements

• 7+ to 15+ years of relevant ASIC physical design experience (depending on degree level).
• Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
• Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre).
• Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Responsibilities

• Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
• Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
• Resolve timing, congestions, EM/IR issues together with Frontend Designers.
• Run Static Timing Analysis (STA) and physical verification.
• Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
• Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
• Partner with architects, logic designers, and analog design team for tapeout readiness.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed