Principal Physical Design Engineer

Celero Communications, Inc. • San Jose, CA

2d • $150,000 - $250,000 • Onsite

About The Position

Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. We are seeking an experienced Physical Design Engineer to lead the transformation of complex circuit designs into high-quality, manufacturable silicon. In this role, you will drive all aspects of the physical implementation flow, including floorplanning, power planning, place-and-route (P&R), clock tree synthesis, timing closure, and physical verification. You will collaborate closely with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet aggressive targets for performance, power, area (PPA), signal integrity, and manufacturability. As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor products.

Requirements

• 5+ years of relevant ASIC physical design experience (depending on degree level).
• Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
• Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre).
• Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Responsibilities

• Own physical implementation of System-on-Chips (SoCs) or complex digital blocks from RTL to GDSII.
• Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
• Resolve timing, congestion, EM/IR issues in collaboration with Frontend Designers.
• Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
• Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
• Partner with architects, logic designers, and analog design teams for tapeout readiness.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: No Education Listed