Principal Hardware Product Manager – PCIe Accelerators & Server Infrastructure

Bolt Graphics•Sunnyvale, CA

3d•$200,000 - $250,000

About The Position

We are looking for a highly technical, execution-oriented Hardware Product Manager to own the product lifecycle and system-level deployment of our disruptive Zeus GPU platform. Moving past legacy architectures, Bolt Graphics is redefining high-performance computing, advanced physics simulation (FP64), and real-time path tracing with a ground-up RISC-V controlled architecture that operates as a standalone computing system. In this role, you will bridge the gap between silicon architecture, system hardware design, and operations to deliver two critical form factors to market: high-density PCIe Gen 5/6 accelerator cards featuring innovative user-expandable memory (LPDDR5X + DDR5 SO-DIMMs) and ultra-scalable 2U HPC Server configurations. You will lead the hardware product definition, manage tier-1 ODM/EMS delivery, and drive the hardware ecosystem required to displace legacy, power-hungry GPU clusters.

Requirements

5+ years of experience defining or engineering high-performance PCIe-based add-in cards (AIC) or complex server systems.
Deep understanding of PCIe Gen 5.0 / 6.0 electrical integrity, form factor constraints, and signal routing.
Strong technical literacy in memory architectures (DDR5, LPDDR5X, or HBM) and an understanding of how large memory capacity scales performance in FP64 scientific simulations (e.g., electromagnetic wave simulations) and path tracing.
Familiarity with embedded processors (RISC-V/ARM), Linux-based system architectures, and network fabrics (Ethernet/InfiniBand) operating at 400Gbps+.
Proven track record of taking complex silicon or hardware hardware products from post-tape-out validation into full production.
Strong business acumen with the ability to build data-driven Total Cost of Ownership (TCO) models, proving the cost and power benefits of Bolt’s architecture against legacy, high-wattage hardware clusters.
BS/MS in Electrical Engineering, Computer Engineering, or a related hardware field.
An MBA is highly valued to successfully bridge complex engineering milestones with customer commercialization strategy.

Nice To Haves

Direct experience working on high-performance compute accelerators, GPUs, or server motherboards designed for render farms and HPC centers.
Experience navigating the hardware ecosystem transition from x86/Arm host controllers to alternative open architectures like RISC-V.
Familiarity with the mechanical and thermal constraints of fitting high-density, multi-slot accelerator boards into standard data center rack infrastructure.

Responsibilities

Form Factor Optimization: Own the PRD and hardware requirements for single/dual-chiplet PCIe accelerator form factors (e.g., Zeus 1c26/2c26) and multi-chip 2U rack-mount server architectures.
Memory Subsystem Strategy: Drive product requirements around our unique, high-capacity expandable memory subsystem, balancing the integration of on-board LPDDR5X with user-upgradable DDR5 SO-DIMM/DIMM slots to unlock up to 2.25TB per server node.
Native Network Integration: Define the roadmap for our integrated, high-bandwidth communication fabrics, utilizing native 400GbE / 800GbE interfaces built directly into the accelerator to eliminate the need for discrete NICs, lowering latency and TCO.
Standalone Subsystem Readiness: Collaborate with firmware and platform teams to ensure the embedded RISC-V control processor seamlessly runs standalone Linux subsystems, including server management features like integrated BMC and IPMI.
Thermal & Power Efficiency: Manage system trade-offs for highly efficient power targets (ranging from 120W single-slot boards up to 500W multi-chip server environments), ensuring optimal balance between air-cooled density and deployment in legacy data center infrastructures.
Silicon-to-System Execution: Drive cross-functional execution from recent chip tape-out through hardware validation, system-level NPI, and mass production.
Supply Chain & Partner Engagement: Partner with hardware engineering, board layout, signal integrity teams, and ODMs to source components, optimize Bill of Materials (BOM) costs, and ensure manufacturing resilience for complex high-speed PCBs.