Principal FPGA Design Engineer

SiTime Corporation•Santa Clara, CA

5d•$148,320 - $203,940

About The Position

SiTime is seeking a seasoned FPGA Architect to lead the design and development of FPGA-based platforms supporting internal testing and validation of its precision, high-performance MEMS timing products. The role develops infrastructure for frequency measurement, low-phase-noise and low-jitter characterization, production, and system-level validation. The successful candidate will own the FPGA lifecycle and provide technical leadership across multiple programs, working with engineering, product, and operations teams.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
At least 10 years of hands-on experience in FPGA architecture and development using Xilinx, Intel/Altera, or similar platforms.
Deep expertise in Verilog or VHDL, simulation tools such as ModelSim or Vivado, and scripting languages such as Python and TCL.
Proven track record designing systems with low jitter, low phase noise, and high signal fidelity.
Strong understanding of timing analysis, clock domain crossing, and high-speed interfaces such as PCIe, DDR, and SERDES.
Experience with lab bring-up, debugging tools such as logic analyzers and oscilloscopes, and test automation.
Demonstrated leadership driving cross-functional initiatives and delivering complex technical programs.
Excellent communication, collaboration, and stakeholder management skills.

Nice To Haves

Experience in MEMS or timing product domains.
Familiarity with hardware/software co-design and embedded systems.
Exposure to production test environments and ATE systems.
Experience presenting technical strategies and outcomes to executive leadership.

Responsibilities

Architect and implement scalable FPGA solutions for internal hardware platforms used in MEMS timing product testing.
Lead cross-functional technical initiatives involving CMOS design, MEMS design, systems and test engineering, validation, and production teams.
Define and drive system-level requirements, ensuring alignment across hardware, software, and test domains.
Own the full FPGA lifecycle, including architecture, RTL design, simulation, synthesis, timing closure, and bring-up.
Develop reusable IP blocks and maintain a modular, maintainable FPGA infrastructure.
Champion design reviews, documentation standards, and continuous improvement practices.
Provide technical leadership and mentorship to junior engineers and influence strategic direction across multiple programs.
Act as a technical liaison between engineering, product, and operations teams to support integration and execution.