Principal FPGA/ASIC Engineer (Onsite)

RTX•El Segundo, CA

8h•Onsite

About The Position

The Principal FPGA/ASIC Engineer will contribute to testbench design, implementation, and verification for high-performance digital ASICs and FPGAs used in signal processing and information assurance products across Mission Systems on the Microelectronics Technology team. The role involves verification environment architecture and design using SystemVerilog with UVM/UVM-F, planning and tracking verification activities, and developing testbenches for RTL blocks. The engineer will also recommend improvements to the ASIC/FPGA verification flow and provide technical leadership for project verification teams, including work planning and status reporting. The position is onsite in El Segundo, California, and requires an active, transferable U.S. government security clearance before the start date. U.S. citizenship is required. The role works with an experienced team and offers exposure to Collins engineering processes and technologies developed internally and by external vendors.

Requirements

RTL coding and simulation experience in VHDL or Verilog.
Testbench development experience for verifying RTL blocks using VHDL and/or SystemVerilog.
Familiarity with best-practice chip-level verification techniques and languages, such as constrained random, functional coverage, and SystemVerilog.
Familiarity with revision-control concepts and tools such as Git or Subversion.
Ability to work with minimal supervision as part of a team with varied skills and backgrounds, while supporting matrixed projects with aggressive schedules and frequent milestones.
Typically requires a STEM degree and at least 8 years of relevant experience, or an advanced degree in a related field and at least 5 years of experience.
Active and transferable U.S. government-issued security clearance required before the start date; current Secret clearance is specified.
U.S. citizenship is required because only U.S. citizens are eligible for the required security clearance.

Nice To Haves

Strong oral and written communication skills, including the ability to document and present work and status.
ASIC/FPGA lab validation experience with advanced lab equipment.
Knowledge of Design for Test (DFT) and manufacturability issues.
Experience with Unix, scripting, C/C++, and/or Perl.
Proficiency with ASIC and/or FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, Vivado, or other FPGA-specific tools.

Responsibilities

Design and architect verification environments using SystemVerilog with UVM/UVM-F.
Create written test plans and test cases, and track code and functional coverage.
Develop testbenches to verify RTL blocks using VHDL or SystemVerilog.
Recommend tools and practices to continuously improve the group's ASIC/FPGA verification flow.
Contribute to engineering estimates for new program pursuits.
Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status.

Benefits

Medical, dental, and vision insurance.
Three weeks of vacation for newly hired employees.
401(k) plan with employer matching funds and a separate employer retirement contribution, including a Lifetime Income Strategy option.
Tuition reimbursement program.
Student Loan Repayment Program.
Life insurance and disability coverage.
Optional pet, home and auto, additional life and accident, critical illness, group legal, and identity theft protection coverages.
Birth, adoption, and parental leave benefits.
Ovia Health, fertility, and family planning benefits.
Adoption Assistance.
Autism Benefit.
Employee Assistance Plan, including up to 10 free counseling sessions.
Healthy You Incentives wellness rewards program.
Doctor on Demand virtual doctor visits.
Bright Horizons child and elder care services.
Teladoc Medical Experts second-opinion program.
Relocation assistance.
Flexible spending accounts.
Flexible work schedules.
Employee Scholar Program.
Paid time off and holidays.
Annual short-term and/or long-term incentive compensation programs may be available, depending on position level and collective-bargaining coverage; payments are not guaranteed.