Principal Engineer, SRAM Compiler & Circuit Design (7820)

TSMC•San Jose, CA

5d•$140,000 - $225,000•Hybrid

About The Position

Step into a pivotal role within our San Jose Design R&D team and position yourself at the forefront of the global semiconductor industry. As a Principal SRAM Design Engineer, you will leverage industry-leading foundry process technologies and design enablement solutions to push the boundaries of silicon performance. This is a hands-on individual contributor (IC) role where you will drive the development of next-generation SRAM compilers and custom memory architectures. You will collaborate closely with our architecture teams to deliver high-impact silicon solutions directly influencing our customers' SoCs. You will join us in our San Jose office, operating on a hybrid work schedule with 4 days in-office.

Requirements

Ph.D. in Electrical Engineering, Computer Engineering, or a related field with 3+ years of industry experience, OR Master’s Degree (MS) with 8+ years of industry experience, OR Bachelor’s Degree (BS) with 12+ years of industry experience.
In-depth, proven track record in SRAM compiler development and custom memory circuit design.
High proficiency in Cadence and Synopsys analog/mixed-signal design environments (e.g., Virtuoso, Spectre, HSPICE, FineSim).
Hands-on experience with design and layout in sub-7nm technologies, specifically TSMC N5 or below.
Strong programming skills in Perl, Shell, TCL, and Python to automate compiler development and characterization flows.

Nice To Haves

Direct design experience with TSMC N3 and below technology nodes.
Deep understanding of advanced Static Timing Analysis (STA), EM/IR-drop analysis, and reliability sign-off.
A proven track record of bringing multi-million gate, complex SoC designs to successful production tape-outs.
Exceptional collaborative mindset, strong communication skills for cross-geography teamwork, and the ability to thrive in a fast-paced, high-pressure R&D environment.

Responsibilities

Drive the hands-on circuit design of cutting-edge SRAM, DRAM, and Non-Volatile Memory (NVM) architectures, including compiler timing/power characterization, netlist/layout tiling, and IR/EM flow execution.
Partner with logic and system architecture teams to define optimal memory specifications and implement custom digital circuits that maximize PPA (Power, Performance, Area).
Lead SRAM compiler verification and Quality Control (QC) flows to ensure robust, silicon-proven compiler deliverables.
Supervise layout execution and compiler coding. Guide the team through silicon bring-up, silicon testing, and the analysis/interpretation of post-silicon test results.
Serve as a key technical liaison between the local San Jose R&D division and HQ in Hsinchu, Taiwan, ensuring seamless technology transfer and alignment.
Act as a versatile technical contributor, taking ownership of both core circuit design and compiler-related automation and infrastructure.