About The Position

Imagine yourself at the center of our hardware development effort. Where you will collaborate with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of talented engineers. As a Custom Design Automation engineer for digital design team, you will perform the following: - Responsible for working on initiatives to automate custom analysis flows for fixing the design margins - Build and maintain memory compiler technologies to facilitate in creating memory arrays in large SoC designs - Debug and provide quick solutions for digital IP designers and/or users. - Define and develop QA checks to verify EDA views of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and timing / power methodologies for SRAM designs - Apply machine learning to optimize flows and QA checks

Requirements

  • BS and a minimum of 10 years of relevant industry experience.

Nice To Haves

  • We are looking for applicants with fundamentals in custom transistor level circuits and SRAM designs
  • Efficient programming skills in languages like: SKILL, Perl, Python, TCL, Shell.
  • Ability to work collaboratively with the circuit team to define and maintain design flows and tools.
  • Solid understanding of industry standard circuit simulator and debug tools, and STA tools.
  • Knowledge of timing, power, noise and EMIR analysis
  • Ability to provide automations for rapid and dynamic design needs.

Responsibilities

  • Responsible for working on initiatives to automate custom analysis flows for fixing the design margins
  • Build and maintain memory compiler technologies to facilitate in creating memory arrays in large SoC designs
  • Debug and provide quick solutions for digital IP designers and/or users.
  • Define and develop QA checks to verify EDA views of SRAM and register files.
  • Collaborate with design and CAD team to optimize design flows and timing / power methodologies for SRAM designs
  • Apply machine learning to optimize flows and QA checks
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