Principal Engineer, PD

GlobalFoundries•Richardson, TX

4d•$153,000 - $265,000

About The Position

The Principal Engineer, SoC PD leads and mentors engineers towards designing and delivering full chip Physical design. This role drives the creation of custom integrated circuits (ICs) from specifications, derive execution level detail and oversee building a solid re-use methodology, enabling fast turnaround through physical design flows and ensuring project efficiency, quality, and innovation. As a leader in Physical Design, you will own and drive all phases of the backend implementation flow for complex SoCs. This includes chip‑level partitioning, synthesis, floorplanning, placement, clock‑tree synthesis, place‑and‑route, timing closure, power and noise analysis, IR/EM reliability, and full physical verification. You will mentor and manage a high‑performing team of RTL‑to‑GDSII physical design engineers, setting technical direction, enabling growth, and ensuring world‑class execution. You will define and deliver ambitious PPA(S) targets through innovation, scalable methodologies, and robust reuse strategies. Collaboration is central to this role—partner closely with cross‑functional teams across DFT, packaging, hardware, program management, IP, and foundry engineering. You will also champion the development, rollout, and adoption of next‑generation EDA tools, flows, and methodologies.

Requirements

Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.
8+ years of industry experience, including: 3+ years in technical leadership roles
Deep hands‑on expertise in end‑to‑end SoC design flows: IP integration, IO ring design, floorplanning, multi‑voltage power planning, data partitioning, MCMM STA, PV, EM/IR, and reliability sign‑off.
Strong proficiency with Synopsys, Cadence, or Siemens/Mentor EDA tools.
Excellent leadership, project management, and communication skills.
Strong analytical mindset with the ability to solve complex timing and power challenges.

Nice To Haves

Exposure to DFT, AMS integration.
Proven track record of delivering custom silicon across diverse application domains.
Inspirational leadership style with a passion for mentoring and scaling high‑performance teams.
Customer‑centric, proactive problem solver.
Passion for continuous learning and driving adoption of industry best practices.

Responsibilities

Own and drive all phases of the backend implementation flow for complex SoCs.
Chip‑level partitioning, synthesis, floorplanning, placement, clock‑tree synthesis, place‑and‑route, timing closure, power and noise analysis, IR/EM reliability, and full physical verification.
Mentor and manage a high‑performing team of RTL‑to‑GDSII physical design engineers, setting technical direction, enabling growth, and ensuring world‑class execution.
Define and deliver ambitious PPA(S) targets through innovation, scalable methodologies, and robust reuse strategies.
Partner closely with cross‑functional teams across DFT, packaging, hardware, program management, IP, and foundry engineering.
Champion the development, rollout, and adoption of next‑generation EDA tools, flows, and methodologies.
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.