Principal Engineer – Physical Design

Microchip • Chandler, AZ

14d • Remote

About The Position

Microchip’s CAD Physical Design (PD) team is looking for a Principal Engineer to work on Full Chip APR/Physical Implementation (Netlist-to-GDSII). In this role you will be working as part of a worldwide team in all areas of Physical Implementation including APR of hierarchical, low power, multi-mode, multi corner mixed signal designs.

Requirements

• Bachelor’s or Masters Degree in Electrical / Electronics Engineering with 10+ years of relevant experience
• Hands-on experience in all aspects of physical design flows such as floor planning, placement optimization, clock tree synthesis, routing, crosstalk avoidance and physical verification
• Advanced knowledge of place and route methodologies.
• Recent experience with leading full chip Physical Design activities.
• Advanced knowledge of VLSI logic principles, clock structures, and design timing closure.
• Advanced knowledge of sign-off tools for Static Timing Analysis, Formal Equivalence, Parasitic Extraction, Power Integrity, and Physical Verification is required
• Knowledge of and experience in UPF and Low Power design practices throughout entire physical design flow.
• Experience with 40nm or 28nm technologies is required
• Proficiency in Tcl and Perl scripting is essential.
• Excellent written and verbal communication skills.
• Excellent problem-solving and debugging skills.
• Self-motivated team player that can collaborate with multiple teams across a geographically diverse company to achieve desired design goals is crucial.

Nice To Haves

• 16nm or smaller technology preferred
• Daily use of ICC/ICC2 or Innovus is preferred.

Responsibilities

• Work on Full Chip APR/Physical Implementation (Netlist-to-GDSII).
• Work as part of a worldwide team in all areas of Physical Implementation including APR of hierarchical, low power, multi-mode, multi corner mixed signal designs.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal