Principal Engineer, Digital IC Design
About The Position
As a Digital IC Design Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. Central Engineering provides IP to be used by all other business groups, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers. This team hires problem solvers and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies. As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs for the CXL product roadmap. Additional responsibilities will include, but not be limited to: Responsible for micro-architecture design and development of SOC and associated component IP like Memory Controllers/PCIE interface/CXL interfaces etc. Working with Architects and Verification engineers to deliver develop complex, high performance and timing critical designs through all aspects of the SoC front-end design flow (incl. timing closure and power optimization).
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience.
- Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
- Strong understanding of SoC architecture, processor cores, memory and peripheral interfaces through hands on prior experience.
- Extensive experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC.
- Hands on experience in interpretive language such as Perl/Python.
- Proven track record of delivering production-quality designs on aggressive development schedules.
Nice To Haves
- Domain expertise in CXL/PCIe protocols, DDR memory controllers is a plus.
Responsibilities
- Lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs for the CXL product roadmap.
- Responsible for micro-architecture design and development of SOC and associated component IP like Memory Controllers/PCIE interface/CXL interfaces etc.
- Working with Architects and Verification engineers to deliver develop complex, high performance and timing critical designs through all aspects of the SoC front-end design flow (incl. timing closure and power optimization).
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
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What This Job Offers
Job Type
Full-time
Career Level
Principal
