Principal Engineer, Digital IC Design
About The Position
The Custom Compute, Storage and Automotive Business Unit provides custom solutions for high performance compute, server, network processing, storage and Automotive applications. CCS&A products employ state-of-the-art custom and industry standard technologies such as CXL, PCIE, Ethernet, and ARM CPU cores. This role involves working with the SOC Integration team to integrate internal and external IP blocks at the chip level, taking ownership of a portion of an SOC design and driving it from initial stages to completion. Responsibilities include collaboration on floorplan, interconnection of IP blocks, static checks, and assisting with subsystem and chip level verification efforts. The engineer will drive to timing closure and collaborate with cross-disciplinary teams including architecture, physical design, chip and block level verification, Design for Test, and packaging to meet all requirements for a high quality, zero-defect product tape-out. The role utilizes industry and internal EDA tools for functional simulations, gate-level simulations, code quality checks, and CDC at the chip level. Additionally, it involves leading design efforts for internally developed processor IP blocks, working closely with verification and implementation teams, delivering micro-architectural specifications, and utilizing/developing automation tools. The position also leverages next-generation AI tools and requires mentoring junior engineers.
Requirements
- Bachelor’s degree in Electrical engineering, Electronics, Computer engineering, or related fields with 10-15 years of experience.
- Master’s degree and/or PhD in Electrical engineering, Electronics, Computer engineering, or related fields with 5-10 years of experience.
- Proven experience in taping out complex SoCs and post silicon debug.
- Strong RTL design skills in SystemVerilog.
- Hands-on experience with SoC integration and debug, along with clock/reset design, CDC, and timing constraints.
- Understanding of how front-end RTL decisions impact physical implementation and verification.
- Familiarity with industry standard ARM protocols (Ex: APB, AHB, AXI, CHI) and SoC interconnect (NOC) architectures.
- Excellent communication skills and ability to participate in problem-solving and quality improvement activities.
- Demonstrates good analytical and problem-solving skills.
- Experience with scripting languages, e.g., Python or Tcl.
- Experience with providing technical leadership to junior engineers.
Responsibilities
- Work with SOC Integration team to integrate internal and external IP blocks at the chip level.
- Take ownership of a portion of an SOC design and drive it from initial stages to completion.
- Collaborate on floorplan.
- Responsibility for interconnection of IP blocks.
- Static checks.
- Assist with subsystem and chip level verification efforts.
- Drive to timing closure.
- Collaborate with cross-disciplinary team including architecture, physical design, chip and block level verification, Design for Test, and packaging to meet all requirements to tape-out a high quality, zero-defect product.
- Use both industry and internal EDA tools to run functional simulations, gate-level simulations, code quality checks, and CDC at the chip level.
- Lead design effort for internally developed processor IP blocks to meet specific architectural needs.
- Work closely with verification and implementation teams to meet product requirements.
- Deliver micro-architectural specifications for these designs.
- Utilize and participate in the development of automation tools to accelerate the pace of development.
- Leverage next-generation AI tools to enhance existing work flows.
- Mentor and guide junior engineers.
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs
- robust mental health resources
- recognition and service awards
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Principal
