Principal Engineer - Digital Design

Microchip Technology Inc.•Chandler, AZ

2d•Onsite

About The Position

Microchip's NCS Team is seeking an experienced Design engineer to support PHY (Physical Layer) development for our next generation of USB products. The role will include working with analog and digital engineers to create mixed-signal IPs and SoC products. As a Principal Digital Design Engineer, the candidate shall be working with multi-sited global Silicon Development Team in the areas of RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design flow. Candidate must be in the Chandler design center.

Requirements

Bachelors degree with at least 10 years of experience in digital design.
Solid, hands-on experience in RTL Coding and functional verification.
Knowledge and experience in Verilog/System Verilog design and test bench creation.
Excellent debug skills in both functional and gate level simulations.
Experience in ASIC design flow including lint checking, Crossing Clock domain checking, DFT methodology, equivalence checking and synthesis.
Hands-on experience with Mentor and Synopsys CAD tools such as Questa, Design Compiler, Formality and Spyglass.
Knowledge in synthesis for defining timing constraints to chip-level integration team and for supporting timing closure for sub-blocks.
Ability to solve timing constraint challenges including asynchronous designs with multiple clock domain crossings and for synchronous designs.
Proficiency in a scripting language such as C, TCL, Perl, Awk, UNIX shell.
Knowledge of revision control tools such as CVS, Perforce, DesignSync, etc. and experience with tagging and release methodology.
Good verbal and written skills.

Nice To Haves

Experience in USB and Ethernet PHY protocols is a strong plus-point.
Experience with Verification methodologies such as UVM/VMM is a desired skillset.
Knowledge of ASIC test methodology such as Stuck-At/At-Speed scan insertion is a plus.

Responsibilities

Support PHY (Physical Layer) development for next generation of USB products.
Work with analog and digital engineers to create mixed-signal IPs and SoC products.
Work with multi-sited global Silicon Development Team in the areas of RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design flow.
Support chip-level integration, verification, and validation teams.
Provide design documentation, description, and information to internal customers.
Work as part of digital, analog, and DSP design team and as part of global multi-sited Development team.
Participate in group meetings, provide project updates, and write functional and technical documents.
Be proactive and willing to learn and adapt quickly in a dynamic and cross-functional environment.