Principal Engineer, Design Verification
Marvell Technology•Westborough, MA
•$178,200 - $263,740
About The Position
As a SoC-level design verification engineer, you will be responsible for the development and maintenance of UVM testbench components and other verification testing collaterals. You will be expected to provide a level of leadership in a team charged with ensuring design quality in a variety of complex SoC architectures.
Requirements
- Experience with Verilog and SystemVerilog, preferably with UVM.
- Experience providing leadership and mentoring in a team setting.
- Basic proficiency with C/C++.
- Experience with scripting languages, e.g., Python or Perl
- Working knowledge of the Linux operating system
Responsibilities
- Analyze architectures and designs to create comprehensive test plans and strategies.
- Organize and lead the development of verification environments and methodologies.
- Develop tests/testing strategies to achieve coverage goals.
- Debug failures and work with designers to resolve issues.
- Help mentor junior engineers in growing their knowledge and skills.
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs
- robust mental health resources
- recognition and service awards
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What This Job Offers
Job Type
Full-time
Career Level
Principal
