Principal Engineer, CAD

SiTime Corporation•Santa Clara, CA

5d•$148,320 - $203,940

About The Position

The Principal Engineer, CAD provides CAD software support for digital, analog and mixed-signal designs using Cadence, Synopsys, Siemens, Keysight and third-party vendor tools. The role supports behavioral, RTL and analog designs; schematic capture; analog/mixed-signal simulation; IC physical design layout; CAD tool customization; Linux; and implementation, testing and deployment of software tools and CAD flows. It also interfaces with EDA vendors and evaluates new software releases before deployment to IC designers across multiple engineering sites. The position owns support for custom CAD flows and PDKs, helps maintain end-to-end tapeout flows, supports design and verification workflows, develops utilities and automation, and provides user support, documentation and training. It diagnoses reported problems and coordinates with vendor application and support teams to resolve issues and influence product improvements. The role requires a BA/BS degree in Electrical Engineering, Computer Science or a related field, at least seven years of experience supporting analog and digital CMOS IC new product development with EDA tools, proficiency with Linux, and experience with specified EDA platforms and programming languages. The position is eligible for a quarterly innovation-goals bonus and equity grants. SiTime offers a 401(k) plan and benefits including medical, dental, vision, life, parental leave, legal services and time-off plans. The posted pay range is $148,320–$203,940 USD.

Requirements

BA/BS degree in Electrical Engineering, Computer Science or a related field.
At least 7 years of experience with analog and digital new product development CMOS IC CAD support using EDA tools.
Experience supporting Cadence Virtuoso Schematic Editor and Layout Suite, Spectre, Spectre-RF, Multi-Mode Simulator, physical layout tools, Assura, PVS, Pegasus, Innovus and Tempus.
Experience supporting Siemens Analog Fast-Spice, Questa, Parasitic CALIBRE PVS and XRC.
Experience supporting Synopsys Design Compiler, VCS, SpyGlass and other tools.
Programming experience with DFII SKILL, PERL, MATLAB, Tcl/Tk, C/C++ and Python.
Proficiency with Linux operating systems, utilities and scripting.
Excellent written and verbal communication skills.
Ability to work collaboratively in a fast-paced team environment.
Strong problem-solving skills, attention to detail and a proactive approach to continuous improvement.

Responsibilities

Provide full lifecycle support for custom CAD flows, including tool development, installation, configuration, maintenance and upgrades across Cadence, Synopsys, Siemens and Keysight platforms.
Own PDK installation, validation, customization, maintenance and release management, keeping versions current and aligned with foundry requirements.
Support and maintain end-to-end tapeout flows, including coordinating and executing foundry submissions and ensuring compliance with foundry requirements, schedules and quality standards.
Support schematic capture, analog and mixed-signal simulation, layout and layout verification software and workflows using revision-controlled processes.
Support and maintain digital simulation, verification environments and digital place-and-route tools.
Develop and maintain CAD utilities, automation scripts and regression flows to improve design efficiency and consistency.
Evaluate new tools through functional evaluation and performance benchmarking, and deploy them.
Provide CAD software and Linux user support for CMOS design engineers and IC layout designers.
Prepare and maintain user documentation, best practices and training materials for design teams across sites.
Diagnose, resolve and regress reported problems in a timely manner.
Interface with EDA vendors’ application and support teams to resolve issues and influence product improvements.
Support additional CAD-related initiatives and projects as assigned.