Principal Engineer - Analog and Mixed-Signal Physical Design

Microsoft•Redmond, WA

12h•$142,800 - $304,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is seeking a Principal Engineer – Analog and Mixed-Signal Physical Design to be a hands-on technical contributor driving physical implementation, timing closure, physical design verification, and custom IP integration for analog and mixed-signal designs. This role is critical for delivering advanced analog and mixed-signal silicon IP on schedule and with high quality, supporting Microsoft's expanding cloud infrastructure and Intelligent Cloud mission. The ideal candidate will possess deep Fusion Compiler-based physical implementation expertise, strong timing closure and physical verification experience, and sufficient custom layout understanding to collaborate effectively with analog design and layout teams while executing critical implementation and debug tasks.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including Microsoft Cloud Background Check.
Requirement to provide proof of country of citizenship or US residency for assessment of eligibility to access export-controlled information, with citizenship verified by a valid passport.
Experience with Fusion Compiler-based APR and physical implementation flows, including floorplanning, placement, clock tree synthesis, routing, optimization, ECO implementation, and closure debug.
Experience with physical design verification, implementation signoff, and silicon quality methodologies.
Experience performing hands-on physical implementation and timing closure for complex silicon IP from concept through tapeout or equivalent silicon development milestones.
Experience leading or coordinating distributed engineering teams, including vendor or external/V-team resources, while remaining directly involved in technical execution.

Nice To Haves

Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field AND 10+ years of technical engineering experience in silicon development, physical design, timing closure, or related disciplines.
Experience with analog and mixed-signal IP physical implementation, custom IP integration, or mixed-signal-adjacent implementation flows.
Knowledge of PrimeTime timing analysis, constraint debug, timing ECO strategy, and timing closure methodologies.
Working understanding of custom analog layout, Virtuoso-based layout methodologies, physical verification, extraction, and layout integration considerations.
Familiarity with advanced-node implementation challenges and cross-functional integration across architecture, circuit design, layout, CAD/methodology, product engineering, and silicon integration teams.
Strong debugging, analytical, problem-solving, communication, and cross-functional collaboration skills.
Proven Principal-level technical leadership across large-scale, cross-functional engineering efforts while remaining hands-on in execution.

Responsibilities

Drive hands-on physical design implementation for analog and mixed-signal IP blocks, including floorplanning, placement, routing, optimization, ECO implementation, and closure debug.
Execute and guide Fusion Compiler-based APR flows, with direct ownership of implementation quality, timing convergence, physical design verification readiness, and signoff closure.
Serve as the technical bridge between analog design, custom layout, physical design, timing, physical verification, CAD/methodology, and silicon integration teams.
Perform timing analysis and closure activities across analog and mixed-signal-adjacent IP, including constraint review, timing debug, implementation tradeoffs, and signoff readiness.
Partner with custom layout engineers to ensure layout feasibility, integration quality, physical verification closure, and timing/implementation convergence without positioning this role as a pure custom layout owner.
Lead internal and external/V-team execution through hands-on technical direction, deliverable review, quality expectations, and schedule alignment.
Debug and resolve complex implementation issues related to physical design, timing closure, extraction, physical verification, layout integration, reliability, and release readiness.
Coordinate implementation activities across architecture, circuit design, layout, CAD/methodology, verification, product engineering, and silicon integration stakeholders.
Contribute to design reviews, implementation quality improvements, signoff planning, and broader execution strategy for analog, mixed-signal, and custom IP physical design deliverables.
Mentor engineers and provide Principal-level technical leadership while remaining directly engaged as a doer in critical implementation and closure work.