Principal Engineer, AI Compiler

Renesas Electronics•San Jose, CA

1d•$150,000 - $230,000•Onsite

About The Position

As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads — from perception and sensor fusion to in-vehicle assistants and advanced driver assistance — are translated into highly optimized, safe, and power-efficient execution on Renesas hardware. This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications.

Requirements

MS/PhD (or equivalent experience) in Computer Science, EE, or related field
Deep experience building AI compilers, accelerator backends, or graph optimization frameworks
Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators
Experience with MLIR, LLVM, TVM‑like systems, or proprietary compiler IRs
Excellent C/C++ and Python skills
Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models)
Strong communication skills are required, e.g. agile development experience in Scrum team (Product Owner or Scrum Master)

Nice To Haves

Experience with automotive or safety‑critical systems
Background in heterogeneous SoCs (CPU/GPU/DSP/NPU)
Performance modeling or hardware–software co‑design experience

Responsibilities

Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration
Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning)
Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies
Partner with SoC and AI accelerator architects to influence hardware features through compiler insights
Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models
Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations)
Mentor senior engineers and set technical direction without people‑management responsibilities