Principal Digital Engineer (DFT Design)

Renesas Electronics•Chandler, AZ

8h•Onsite

About The Position

This is an opportunity to join a top-notch Power Management IC Team with Renesas leading Automotive Business Unit. You will be part of a very skilled group of engineers who are helping build world-class automotive PMIC products that will power tomorrow’s automobiles. You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design – from writing specifications to developing tests for mass production. You will be a key contributor to the digital DFT design team and work closely with the digital design team for meeting TEST requirements for Automobile and work closely with test engineering teams for validating the test patterns and meeting ASIL-B/D requirements. You will have an opportunity to work on new designs, insert Lbist and shape the company’s pathway for success.

Requirements

Masters plus 12+ years or Bachelors plus 15+ years experience in digital design and DFT implementation.
Must be a team player and yet be an independent thinker with strong digital design and DFT fundamentals
Hands on experience in Scan insertion, improving scan coverage, ATPG, experience in Logicbist insertion during synthesis or rtl.
Gate level simulations with test patterns, delivering test patterns to Test engineering team and work closely with them to get the patterns validated.
Must have basic digital RTL coding experience besides synthesis exposure.
Must have experience with at least 8 tapeouts with hands on experience with DFT/Scan.
Ideal candidate will have solid understanding of synthesizable design, timing constraints and exceptions.
Must have experience with industry standard Synopsys, Cadence, Mentor, Siemens for scan, Lbist insertion and ATPG. Tetramax experience is a huge plus.
Attention to detail, accuracy and expertise in DFT required.
Must have good written and verbal cross-functional communication skills
Have an analytical mind - be open to new ideas and have capability to persuade others in convincing and implementing better flows and processes.

Nice To Haves

Mixed signal experience highly preferred.
Exposure to automotive test requirements, ASIL, is highly preferred.

Responsibilities

Inserting DFT/Scan on digital logic, ATPG, validating test patterns on pre and post layout gate level netlist.
Delivering test patterns to TEST engineering team and validating them on silicon.
Inserting Logicbist with industry standard tools.
Improving scan coverage and modifying RTL for scan.
Reduce ATE tester time by reducing scan patterns while achieving the required coverage.
Participate in all aspects of digital design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog coding, DFT insertion, generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC.
Working closely with Architects, Design, P&R, Test and Silicon validation teams.
Assisting with top level test-bench creation for scan and running gate level simulations.
Debug scan pattern fails on ATE and fix the scan patterns.
Writing detailed design documents and help writing DFT specifications, reviewing the specs with different stake holders and own the design to meet the spec.
Organizing and participating in key design reviews and completion of various checklists.