DFT Design Engineer

Cadence Design Systems • San Jose, CA

1d

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for the candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. We’re doing work that matters. Help us solve what others can’t.

Requirements

• US citizenship preferred
• Prior 3-12 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
• Intimate knowledge of DFT insertion flows
• Basic scan chain insertion using synthesis or other software tools
• Experience in compression scan insertion, LBIST and other scan technologies
• Intimate knowledge of memory build-in self-test (MBIST)
• Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
• Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
• Ability to work in collaborative team environment
• Should be able to finish DFT tasks independently
• Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems
• Self-driven and committed individual who can work in a fast-paced project environment

Nice To Haves

• Hands-on knowledge of synthesis, verification and debugging Verilog testbenches
• Knowledge of timing analysis and equivalency checks would be added bonus
• Prior experience with Cadence tools and flows is highly desirable

Responsibilities

• Scan chain insertion
• Compression scan insertion
• MBIST insertion
• ATPG pattern generation
• Debug and Analysis of failures to improve fault coverage
• Verification of ATPG testbenches and debugging root cause of simulation mis-compares
• Work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed