Principal Digital Design Engineer

Marvell Technology • Ottawa, ON

36d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. This is an existing vacancy. Your Team, Your Impact About Marvell At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better. The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below. The Opportunity Optical PHY BU develops cutting-edge optical Ethernet Transceiver ASICs. Current online working and meetings that are through mediums such as Zoom and Webex are all based on cloud services. In order to respond to the dramatically increased demands of cloud-based connection capability, major cloud computing companies urgently demand faster and more secure internet connection components. One critical part of that component includes the optical ethernet transceiver ASICs. As a member of a digital hardware development team, the candidate will be assisting in chip design, verification, supporting back-end teams and timing closure.

Requirements

• Bachelor’s degree in Electrical Engineering or related fields and 10+ years of related professional experience.
• Experience of entire design cycle from micro-architecture specification definition, verilog coding, constraint development, synthesis, LEC and timing closure to post-silicon debug and support in lab environment.
• Experience with power and latency optimization.
• Experience in both RTL development (block and subsystem level) and gate level verification and debug.
• Experience with matching DSP block model functionality with RTL, synthesis, static timing analysis and functional verification
• Experience in high speed IEEE compliant DSP physical layer products preferred
• Experience with chip bring up and functional validation of the product in the lab
• Strong system level modeling, debugging and troubleshooting
• Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment.
• Team player
• Effective communication and presentation skills
• Strong language user in Verilog, System Verilog, Python, Unix Shell.

Responsibilities

• High speed data path RTL implementation using Verilog, synthesis and backend resources
• Integrate vendor IP and support
• Well versed with the complete ASIC flow from micro-architecture to customer deployment
• Post-silicon debug and correlation.
• Specify and implement digital features of a chip.
• Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification.
• Develop ASIC specification and micro-architecture of signal processing and communications algorithms
• Assist in design automation of various aspects of the CAD EDA flow.
• Mentorship of junior team members

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level