Principal Digital Design Engineer

PowerLattice Technologies Inc•Vancouver, WA

13h•Hybrid

About The Position

We are seeking a highly skilled and hands-on Principal Digital Design Engineer to drive the microarchitecture, design, and implementation of complex digital systems and SoC components. This role combines deep technical contribution with team leadership, requiring active involvement from microarchitecture definition through RTL development and into back-end implementation and silicon bring-up.

Requirements

Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
10+ years of experience in digital design with significant hands-on RTL development
Proven track record of delivering complex SoC or subsystem designs to tapeout
Strong expertise in: RTL design and microarchitecture
SoC integration and standard interfaces
Hands-on experience with back-end flows, including: Scan insertion and DFT (scan, MBIST, test coverage)
Logic equivalence checking (LEC)
Static timing analysis (STA) and timing closure
Timing constraint development and debug (SDC)
Solid understanding of: Clocking, resets, CDC/RDC, and low-power design
Synthesis and physical design implications
Experience with industry-standard EDA tools (Synopsys, Cadence)
Experience with low-power methodologies (UPF/CPF)
Strong debugging and problem-solving skills

Nice To Haves

Familiarity with advanced technology nodes and implementation challenges
Experience with formal verification techniques
Experience with silicon bring-up and post-silicon debug

Responsibilities

Define microarchitecture for complex digital blocks and subsystems
Actively contribute to RTL development for key components
Drive design tradeoffs across performance, power, area (PPA), and testability
Write, review, and integrate high-quality RTL
Lead block- and chip-level integration, resolving interface and system issues
Ensure designs are clean for lint, CDC/RDC, and synthesis
Ensure RTL is optimized for synthesis, timing, and physical design
Work on scan insertion, test architecture, and coverage closure
Perform, review and debug logic equivalence checking (LEC) results between RTL and netlists
Define and validate timing constraints (SDC) and complete timing closure
Drive and implement timing and functional ECOs as needed
Drive signoff readiness including lint, CDC/RDC, synthesis, LEC, and timing checks
Ensure designs meet functional, timing, power, and test requirements
Support silicon bring-up, debug, and root-cause analysis
Work closely with verification, physical design, DFT, and firmware teams
Align design decisions with verification plans and implementation
Act as the technical bridge between front-end and back-end teams