Principal Digital Design Engineer / Chip Lead

Micron Technology • Minneapolis, MN

1d

About The Position

Micron's Interface Pathfinding team operates at the leading edge of innovation, driving performance-scaling across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions. As the Digital Design Engineer / Chip Lead, you will be the technical anchor of a deliberately small, senior team whose collective experience spans world-class analog and digital design, decades of hands-on layout, silicon characterization, and physical design and design verification — united around the goal of carrying high-speed interface innovations from architecture to tape-out.

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
• 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or senior designer role
• Expert-level proficiency in SystemVerilog RTL design and coding best practices
• Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus)
• Proficiency with industry-standard RTL simulation and debug tools (VCS, Xcelium, or equivalent; Verdi or DVE for waveform debug)
• Solid understanding of CDC analysis methodologies and tools (SpyGlass, JasperGold CDC, or equivalent)
• Demonstrated experience integrating hard and soft IP blocks in a mixed-signal or PHY-adjacent chip environment
• Ability to work effectively as a technical lead on a small team — comfortable making decisions with incomplete information and owning the outcomes
• Strong written communication skills — this role produces specifications, not just code
• Experience partnering with design verification teams to define verification plans, review coverage metrics, and drive closure of functional and corner-cases prior to tape-out.
• Proficiency in leveraging AI for productivity.

Nice To Haves

• Experience with high-speed PHY architectures (SerDes, DDR, or equivalent analog I/O structures)
• Familiarity with I2C management bus architecture, Eye Monitor control logic, or PRBS-based error counting implementations
• Experience with DFT strategy definition including scan insertion, ATPG planning, and boundary scan for high-speed I/O
• Familiarity with OTP/fuse-based trim and calibration architectures for PHY analog parameters
• Prior experience in a small team or startup-like environment where role boundaries are defined by need rather than org chart

Responsibilities

• Define top-level chip architecture, partition responsibilities across hard and soft IP blocks, and own the integration of hard macros alongside third-party soft IP.
• Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control blocks, CSR/register file, clocking control logic, and top-level integration.
• Develop and own chip-level timing constraints (SDC), define clock domain crossing strategy, and provide timing budgets per block to the Physical Design engineer.
• Drive logic synthesis (DC / Genus) and guide optimization for PPA targets across all design blocks.
• Partner with DV staff to apply assertion-based verification, coverage-driven verification, formal methods and constrained-random techniques to ensure high quality verification of control logic, interfaces, and system behaviors.
• Define interfaces between PHY hard macro, third-party soft IP, and internally designed blocks; manage IP integration agreements and vendor coordination.
• Own and drive the tape-out checklist sign-off process, coordinating across Physical Design, Verification, and analog team members to achieve clean handoff to the foundry.
• Author architecture specifications, block-level design specifications, and interface control documents that serve as the authoritative reference for the team.
• Capture design decisions, lessons learned, and architectural rationale to accelerate follow-on chip development.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Principal