Principal DFT Engineer
About The Position
The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale. SambaNova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets. About the role Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence. We are looking for a highly hands-on engineer who will be responsible for DFT architecture and implementation, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips
Requirements
- B.S. in computer science, computer engineering, or related field
- 10+ years relevant industry experience
- Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG, and hierarchical DFT
- Hands-on experience with Siemens Tessent tool flow (preferred) or equivalent industry standard DFT tools
- Strong understanding of advanced ATPG, silicon diagnosis, and failure localization methodologies
- Experience with STA constraints & analysis for DFT modes & SDF simulations
- Working knowledge of Verilog/System-Verilog simulators & waveform debugging
Nice To Haves
- Familiarity with cell-aware ATPG, small-delay defects, IEEE 1500, IEEE 1687/IJTAG, and low-power DFT is highly desirable
- Experience with ATE pattern deployment and silicon bring-up
- Experience with multi-die/chiplet DFT, known-good-die test, or die-to-die interface testing
- Experience with large compute, AI accelerator, or HPC SoCs
Responsibilities
- Define & implement block-level and SoC-level DFT architecture for large, hierarchical SoCs
- Develop and maintain ATPG flows for stuck-at, at-speed and advanced fault models.
- Develop scripts and automation for DFT insertion, ATPG, coverage analysis, pattern generation, and debug.
- Develop and maintain JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure for internal test and debug access.
- Generate production-quality ATPG and MBIST patterns and support deployment to ATE.
- Work closely with STA and Physical Design teams on DFT timing closure
- Support silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization.
Benefits
- Competitive total rewards package, including base salary, equity, and benefits
- 95% premium coverage for employee medical insurance
- 77% premium coverage for dependents
- Health Savings Account (HSA) with employer contribution
- Dental insurance
- Vision insurance
- Short/Long term Disability insurance
- Basic Life insurance
- Voluntary Life insurance
- AD&D insurance
- Flexible Spending Account (FSA) options (Health Care, Limited Purpose, and Dependent Care)
- Full subscription to Headspace
- Gympass+ membership with access to physical gyms
- One Medical membership
- Counseling services with an Employee Assistance Program
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What This Job Offers
Job Type
Full-time
Career Level
Principal
Education Level
Associate degree
