Principal Design Engineer

Lattice Semiconductor•San Jose, CA

4d•$248,400

About The Position

We are seeking a Principal Design Engineer, passionate individual with technical leadership capabilities to build complex system designs for Configuration, Security, Processor, Memory and High-Speed interfaces based on application requirements. The individual should be able to translate system requirements and architectural specifications into micro-architecture and implementation. The individual should have the ability to provide technical insights for engineering teams, provide continuous improvement in IP performance and ease-of-use in system integration.

Requirements

20 years experience of hardware IP and integration design
Led a team of cross-functional engineers across multiple sites/geos
Led multiple programs from concept to Tape Out and production release
Expertise in System Verilog, Synthesis, and Static Timing Analysis
Good understanding of DFx (test and debug) methodology on IP and chip level
Ability to debug complex issues with floor-planning, power distribution network, system level clocking, timing closure and SIPI
Deep experience in one or more of following domains: High speed interfaces (LPDDR5, USB4.0, Chip-to-Chip interconnects), System Interconnects (Coherent NoC, AMBA), processors (ARM, MIPS, RISC-V) and FPGA systems
Experience debugging complex system level use cases through verification, emulation and system validation
Programming skills (e.g.: C/C++, Perl, TCL or Python) and proficient in using GenAI and agentic AI methodologies for scaling design
Strong written and oral communication skills.
Frequent presentations to executive leadership on status of projects and roadmaps
Ability to drive IP roadmap with deep engagement with leading IP vendors and execute competitive analysis and benchmarking
The ability to stay on top of latest advancements in technology, design and AI
BS/MS/PhD in Electronics or Computer Engineering minimum of 20 years of FPGA/SoC design experience.
Independent and self-motivated, capable of executing under dynamic environment and uncertainties

Responsibilities

Build complex system designs for Configuration, Security, Processor, Memory and High-Speed interfaces based on application requirements.
Translate system requirements and architectural specifications into micro-architecture and implementation.
Provide technical insights for engineering teams.
Provide continuous improvement in IP performance and ease-of-use in system integration.
Debug complex issues with floor-planning, power distribution network, system level clocking, timing closure and SIPI.
Debug complex system level use cases through verification, emulation and system validation.
Drive IP roadmap with deep engagement with leading IP vendors and execute competitive analysis and benchmarking.
Stay on top of latest advancements in technology, design and AI.