Principal Deep Learning Communication Architect

NVIDIA•Austin, TX

6d•$272,000 - $431,250

About The Position

NVIDIA is seeking a Principal Deep Learning Communication Architect to lead the architecture and development of communication libraries for next-generation platforms. The role defines long-term technical roadmaps and helps AI models scale across clusters comprising hundreds of thousands of nodes. It focuses on communication primitives and collective algorithms optimized for heterogeneous interconnects, including NVLink, Spectrum-X Ethernet, and Quantum-X InfiniBand. The architect will work with application developers to co-design specialized communication primitives and ensure AI and HPC libraries—including NCCL, NIXL, NVSHMEM, UCC, and UCX—meet the needs of trillion-parameter models and Agentic AI. The position also collaborates with silicon architects and software engineers on future networking hardware specifications and develops analytical models and simulators to predict system behavior under emerging workloads. The role requires a Ph.D. or M.S. in Computer Science, Electrical Engineering, or a related field, or equivalent experience, and 12 or more years of industry experience in HPC or distributed deep learning. NVIDIA offers a base salary range of $272,000–$431,250, determined by location, experience, and other objective job-related factors, as well as equity and benefits. Applications will be accepted at least until November 3, 2026.

Requirements

Ph.D. or M.S. in Computer Science, Electrical Engineering, or a related field, or equivalent experience.
12+ years of industry experience in high-performance computing (HPC) or distributed deep learning.
Deep understanding of 3D parallelism (Data, Tensor, Pipeline) and advanced strategies including Context Parallelism, Expert Parallelism, and Zero Redundancy Optimizer (ZeRO) variants.
Deep technical proficiency with NCCL, UCX, UCC, NVSHMEM, or MPI.
Experience with RDMA, RoCE, and low-level InfiniBand verbs.
Advanced knowledge of high-throughput inference engines and schedulers, specifically TensorRT-LLM, vLLM, SGLang, and NVIDIA Dynamo.
Expert knowledge of the NVIDIA GPU memory hierarchy, including HBM3e/HBM4 and L2 cache, and CUDA programming models.

Nice To Haves

Hands-on experience developing within Megatron-Core, DeepSpeed, or JAX/XLA, with understanding of how these frameworks interact with low-level communication runtimes.
Significant upstream contributions to major open-source projects such as PyTorch Distributed, KServe, or Ray.
A proven track record of deploying and optimizing models on NVIDIA platforms or similar rack-scale systems.
A strong portfolio of patents or papers in top-tier systems and architecture venues such as ISCA, ASPLOS, NeurIPS, or SC.

Responsibilities

Define the long-term technical roadmap for communication libraries across NVIDIA’s next-generation platforms, enabling models to scale across clusters comprising hundreds of thousands of nodes.
Lead development of next-generation communication primitives and collective algorithms optimized for heterogeneous interconnects such as NVLink, Spectrum-X Ethernet, and Quantum-X InfiniBand.
Partner with application developers to architect and implement specialized communication primitives, and evolve AI and HPC libraries including NCCL, NIXL, NVSHMEM, UCC, and UCX for trillion-parameter models and Agentic AI.
Collaborate with silicon architects and software engineers to influence specifications for next-generation networking hardware.
Develop high-fidelity analytical models and simulators to predict system behavior under emerging workloads.