Principal ASIC Architect

Tensordyne•Sunnyvale, CA

6d•Hybrid

About The Position

Tensordyne (formerly Recogni) AI is reshaping our world, performing cognitive tasks once unique to humans—perceiving across modalities, learning quickly, and solving complex problems. Tensordyne builds high-performance, low-power generative AI inference systems. We’re leveraging novel techniques from the latest AI research to build custom silicon, hardware, and software to accelerate multimodal generative AI at scale—delivering safe, sustainable, cutting-edge solutions for hyperscaler and neocloud data centers. Headquartered in Sunnyvale, CA, and Munich, Germany, with remote team members across North America and Europe, Tensordyne is a well-funded, fast-moving startup. We support our people with competitive pay, comprehensive benefits, flexibility, and recognition programs—because breakthrough technology starts with a healthy, empowered team. Come join us, as we shape the future of AI together! The Opportunity: In this role, you will lead all phases of ASIC architecture definition and design of Tensordyne’s next-generation family of processors for generative AI inference acceleration. This is an exciting opportunity that involves high-level silicon architecture planning, hands-on design, prototyping of ASIC design concepts, mentoring, and technical leadership to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne’s vertically integrated, generative AI inference acceleration systems for data centers.

Requirements

15+ years of hands-on experience and deep expertise in silicon design engineering and architectural planning of high performance compute (HPC) processors like GPUs, CPUs, TPUs etc., as well as HBM and high speed SerDes networking technologies for AI workloads.
Strong understanding of generative AI algorithms, attention mechanisms, foundation transformer models, and mapping these functions to hardware.
Strong Verilog programming skills, and experience with RTL verification, and performance modeling.
Experience with performance analysis, debugging, and optimization is also required.
Track record of developing architectural C-models, SystemC, or TLM.
Expert-level skills in C/C++, and scripting languages like Python or Perl for automation and modeling.
An MS or PhD in Electrical Engineering, Computer Engineering or related engineering discipline.

Responsibilities

Lead the architectural planning and definition of new Tensordyne AI processors, that consist of highly specialized floating point AI compute cores, embedded memory, embedded RISC-V CPU cores, and high speed serial communications with chip-to-chip networking fabric, HBM, and PCIe connectivity.
Analyze technical needs, propose chip design solutions, create detailed design specifications, lead architectural modeling and establish ASIC development milestones to ensure that the final product meets requirements related to functionality, inference performance, inference accuracy, power efficiency, programmability, debuggability and manufacturability.
Work closely with external engineering partners, ASIC design engineers, ASIC design verification teams, SOC physical design teams, interdisciplinary software teams, product management and executives, providing technical guidance, overseeing design reviews and mentoring where applicable.
Lead the evaluation of new silicon IP technologies, EDA tools and methodologies to enhance the product and improve the efficiency of our chip design process.