Principal Application Engineer- Timing Sign Off

Synopsys•Sunnyvale, CA

74d•$160,000 - $240,000•Onsite

About The Position

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You have spent a decade or more in the trenches of timing signoff, and you know that the moment a customer says "we're ready to tape out" is when the real work begins. The difference between a chip that ships on schedule and one that doesn't often comes down to someone who can diagnose a cryptic timing violation at 2 a.m., propose a workaround that doesn't blow up the methodology, and explain the tradeoff clearly enough that the design lead trusts it. You are fluent in PrimeTime the way some people are fluent in a second language. You have debugged enough corner case failures to know when a problem is tool behavior, user error, or an actual design issue, and you can tell the difference in about ten minutes. When a customer hits a wall three days before tapeout, you do not panic. You ask the right questions, pull the right data, and find a path through. You have worked closely enough with product teams to know what belongs in a feature request and what belongs in a methodology guide. Mentoring comes naturally to you because you remember what it felt like not to know, and you care about making the next engineer better. At Synopsys, you will work with the most advanced chip designs in the world, and what you enable will directly determine whether those chips make it to market.

Requirements

Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field
10+ years of hands-on experience with timing analysis and signoff tools, flows, and methodologies in a customer-facing or product development role
Deep working knowledge of PrimeTime, and direct experience with at least two of the following: PrimeShield, PrimeClosure, PrimePower
Demonstrated ability to debug complex signoff issues under tapeout pressure and propose solutions that balance accuracy, runtime, and methodology constraints
Strong understanding of static timing analysis fundamentals, including multi-mode multi-corner analysis, OCV, AOCV, path-based analysis, and signoff closure techniques
Experience with adjacent tools like StarRC, RedHawk-SC, Spice, Hspice, or PrimeSim is a strong plus
Proven ability to work effectively across global teams, including product engineering, account management, and customer design teams in different time zones

Responsibilities

Support customer tapeouts for leading edge designs, diagnosing timing, power, and signoff issues in PrimeTime, PrimeShield, PrimeClosure, and PrimePower under real schedule pressure
Deploy newly developed signoff features with customers, working through beta testing, adoption blockers, and methodology integration in live design environments
Evaluate customer requirements and translate them into actionable enhancement requests for the product development team, backed by real use cases and data
Build and deliver technical training content, demos, and methodology documentation that help customers and internal teams use signoff tools correctly and confidently
Replicate, debug, and escalate product issues, working across engineering, R&D, and account teams to resolve problems that affect customer schedules
Mentor applications engineers and customer design teams on timing signoff best practices, corner case handling, and flow optimization
Align technical enablement plans with account strategy, ensuring that the right customers get the right support at the right stage of their design cycle