Principal Analog Design Engineer

Neurophos • San Mateo, CA

3d • Onsite

About The Position

Neurophos is seeking a seasoned Principal Analog Design Engineer to play a vital role in developing cutting-edge full-custom electronic transceiver components that interface directly with our custom silicon photonics and are essential to our revolutionary photonic AI platform. You will be responsible for the full lifecycle of analog blocks, from specification and architecture down to tape-out-ready layout. Success in this role requires a deep understanding of transistor-level circuit design, linearity, noise performance, and signal integrity in CMOS processes up to GHz speeds. If you possess a proven track record of designing robust, ultra-fast analog circuits and are eager to work at the intersection of electronics and photonics, you will make a defining impact on the future of optical computing.

Requirements

• MS or PhD in Electrical Engineering.
• 10+ years of professional experience in full-custom analog integrated circuit design
• 5+ years of dedicated experience in either GHz-speed RF or GHz-speed broadband analog design.
• Demonstrated expert proficiency in the Cadence tool suite, specifically Virtuoso schematic, simulation, and custom layout.
• Deep understanding of semiconductor device physics, linearity, noise analysis, and high-frequency circuit theory.
• Proven track record of taking high-speed analog blocks from concept to mass production (successful tape-outs).

Nice To Haves

• A background in photonic transceivers or optical communication electronics.
• Extensive design experience in TSMC latest technology nodes, such as N5P, N3P, and N2P.
• Experience designing high-speed data converters.
• Experience designing low-jitter clocking circuits, including PLLs.
• Proficiency in electromagnetic simulation tools such as EMX or HFSS.
• Experience with frequency domain simulation in Spectre RF.

Responsibilities

• Design, simulate, and verify high-speed analog circuits, including but not limited to high-swing drivers, transimpedance amplifiers, ADCs, DACs, and PLLs, in deep-submicron CMOS technologies.
• Define architecture and specifications for electronic blocks based on system-level requirements.
• Perform full-custom schematic capture, advanced analog simulations, and complete physical layout, including DRC/LVS, of critical analog blocks using Cadence Virtuoso.
• Ensure rigorous signal integrity and power integrity across all high-speed interconnects.
• Conduct layout floor planning.
• Conduct post-layout extraction and simulation to validate performance against parasitic effects.
• Collaborate closely with the Photonics and Digital teams to optimize the electro-optic interface, maximizing performance across the combination of disciplines.
• Collaborate with team members to prepare and conduct the bench characterization and production tests.

Benefits

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO.
• 401(k) matching
• stock option opportunities
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior