Principal AI Silicon Architect

Microsoft • Redmond, WA

1d • $165,600 - $331,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops the infrastructure and foundational technologies powering Microsoft's cloud businesses and Azure platform. The AI Silicon Architecture team defines and delivers operational measures of success for hardware manufacturing, improving planning, quality, delivery, scale, and sustainability for Microsoft cloud hardware.

The Principal AI Silicon Architect will own end-to-end power architecture for high-power AI accelerator SoCs, considering tradeoffs across the SoC, package, board, and system. The role defines power-management architectures and high-power operating approaches, translates workload and product requirements into power budgets and architectural targets, and collaborates across engineering disciplines from early architecture through deployment. The architect provides technical leadership through specification, design reviews, implementation decisions, silicon bring-up, characterization, and optimization.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 7+ years of technical engineering experience; or master's degree in one of these fields and 10+ years of experience; or bachelor's degree in one of these fields and 12+ years of experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Ability to satisfy export-control eligibility requirements for access to controlled information, including providing documentation to verify citizenship, U.S. residency, or another protected status; citizenship is verified with a valid passport, with other documents applicable for lawful permanent residents, refugees, and asylees.

Nice To Haves

• Significant industry experience in SoC power architecture, power delivery, power management, power integrity, or a closely related area, particularly with high-performance or high-power SoCs.
• Experience architecting and optimizing power delivery across silicon/SoC, package, board, and power supply.
• Demonstrated ability to make complex architectural tradeoffs involving performance, power, thermal behavior, reliability, cost, and implementation complexity.
• Deep knowledge of high-power SoC power-delivery architecture, including package and board power-delivery network (PDN) design and optimization.
• Deep understanding of power integrity, voltage droop, transient response, current delivery, power rails and domains, and interactions between workload behavior and PDN design.
• Experience defining package-level and SoC-level power architecture for large, high-performance silicon.
• Understanding of voltage/frequency scaling, DVFS, clock gating, power gating, power states, workload-aware power management, and energy-efficiency optimization.
• Experience with silicon, package, and board co-design and making system-level rather than locally optimal power decisions.
• Experience with AI accelerators, GPUs, HPC processors, server CPUs, or other very high-power datacenter-class silicon.
• Experience analyzing workload power characteristics and translating them into power-delivery and power-management requirements.
• Experience with multi-die or chiplet architectures and managing power across multiple dies and power rails.
• Understanding of the interaction between power delivery, thermal design, reliability, performance, and system design.
• Proven ability to influence architecture across organizational boundaries and communicate complex tradeoffs to implementation teams and senior technical leadership.

Responsibilities

• Own end-to-end power architecture for high-power AI accelerator SoCs, analyzing tradeoffs across the SoC, package, board, and system.
• Define SoC- and package-level power-management architecture, including power and voltage domains, DVFS, clock and power gating, low-power states, workload-aware power management, and other power-saving mechanisms.
• Define architectures for high-power operating conditions, including workload power excursions, peak and sustained power, transient behavior, and power and thermal constraints.
• Partner with performance and workload teams to understand workload characteristics and identify opportunities to improve performance per watt and system-level efficiency.
• Drive architectural tradeoffs involving performance, power, power-delivery capability, thermal limits, reliability, area, cost, and implementation complexity.
• Translate workload and product requirements into system- and silicon-level power budgets, design targets, and architectural requirements.
• Define SoC-to-system interfaces and control mechanisms for power, thermal, and platform management.
• Collaborate with SoC architecture, physical design, package, board and system, power delivery, thermal, firmware, platform, manufacturing, and validation teams from early architecture through product deployment.
• Provide technical leadership throughout the development lifecycle, including architecture specification, design reviews, implementation tradeoffs, silicon bring-up, characterization, and optimization.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal