Principal AI Silicon Architect

Microsoft • Mountain View, CA

1d

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) delivers infrastructure and foundational technologies for Microsoft’s online businesses and Azure platform. The AI Silicon Architecture team helps define and deliver measures of success for cloud hardware manufacturing, improving planning, quality, delivery, scale, and sustainability. The team is seeking a Principal AI Silicon Architect to develop customer-focused technical solutions for Microsoft’s cloud infrastructure.

The role owns end-to-end power architecture for high-power AI accelerator SoCs, considering the SoC, package, board, and system. It defines SoC- and package-level power-management architecture and high-power operating approaches, and drives system-level tradeoffs among performance, power delivery, thermal limits, reliability, area, cost, and implementation complexity. The architect translates workload and product requirements into silicon and system power budgets and requirements, and defines SoC-to-system interfaces and controls for power, thermal, and platform management.

The position collaborates with architecture, physical design, package, board and system, power delivery, thermal, firmware, platform, manufacturing, and validation teams from early architecture through deployment. It provides technical leadership through specification, design reviews, implementation decisions, silicon bring-up, characterization, and optimization.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 7 years of technical engineering experience; or a master's degree in one of these fields and at least 10 years of experience; or a bachelor's degree in one of these fields and at least 12 years of experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Must satisfy export-control eligibility requirements for access to controlled information and provide proof of citizenship, U.S. residency, or other protected status; citizenship or status will be verified using applicable documentation.
• Significant industry experience in SoC power architecture, power delivery, power management, power integrity, or a closely related area, with experience on high-performance or high-power SoCs.
• Demonstrated experience architecting and optimizing power delivery across silicon/SoC, package, board, and power supply levels.
• Demonstrated ability to make complex architectural tradeoffs involving performance, power, thermal limits, reliability, cost, and implementation complexity.
• Deep knowledge of high-power SoC power-delivery architecture, including package and board power-delivery network design and optimization.
• Deep understanding of power integrity, voltage droop, transient response, current delivery, power rails and domains, and the interaction between workload behavior and power-delivery network design.
• Experience defining package- and SoC-level power architecture for large, high-performance silicon.
• Understanding of voltage/frequency scaling, DVFS, clock gating, power gating, power states, workload-aware power management, and energy-efficiency optimization.
• Experience with silicon, package, and board co-design and making system-level power decisions.
• Experience with AI accelerators, GPUs, HPC processors, server CPUs, or other very high-power datacenter-class silicon.
• Experience analyzing workload power characteristics and translating them into power-delivery and power-management requirements.
• Experience with multi-die or chiplet architectures and managing power across multiple dies and power rails.
• Understanding of the interactions among power delivery, thermal design, reliability, performance, and system design.
• Ability to influence architecture across organizational boundaries and communicate complex tradeoffs to implementation teams and senior technical leadership.

Responsibilities

• Own end-to-end power architecture for high-power AI accelerator SoCs, analyzing tradeoffs across the SoC, package, board, and system.
• Define SoC- and package-level power-management architecture, including power and voltage domains, DVFS, clock and power gating, low-power states, workload-aware power management, and other power-saving mechanisms.
• Define architectures for high-power operating conditions, including workload power excursions, peak and sustained power, transient behavior, and power and thermal constraints.
• Partner with performance and workload teams to understand workload characteristics and identify opportunities to improve performance per watt and system-level efficiency.
• Drive architectural tradeoffs across performance, power, power-delivery capability, thermal limits, reliability, area, cost, and implementation complexity.
• Translate workload and product requirements into system- and silicon-level power budgets, design targets, and architectural requirements.
• Define SoC-to-system interfaces and control mechanisms for power, thermal, and platform management.
• Collaborate with SoC architecture, physical design, package, board and system, power delivery, thermal, firmware, platform, manufacturing, and validation teams from early architecture through product deployment.
• Provide technical leadership throughout the development lifecycle, including architecture specifications, design reviews, implementation tradeoffs, silicon bring-up, characterization, and optimization.

Benefits

• Certain roles may be eligible for benefits and other compensation; additional benefits and pay information is available via the Microsoft careers website.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal