Power Performance Modeling Engineer - Platform Architecture
About The Position
At Apple, products are holistically designed to deliver an unrivaled customer experience. SoC hardware, Systems, and Software architectures are co-optimized and tuned for high performance and operating efficiency. Engineers use Constrained Performance Models to analyze and refine architecture and implementation. These models simulate overall performance and efficiency of Apple System on Chip (SoC) in the presence of electrical, thermal, and reliability constraints and control systems. In this highly visible role, the Constrained Performance Modeling Engineer drives development of these simulators and collaborates with a cross-functional team of SoC, System, and Software Architects to influence the design of future Apple products.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related engineering field.
- Experience in high-performance and low-power microprocessor architecture and design techniques.
- Experience coding in C, Python, or similar programming languages.
Nice To Haves
- 10 or more years of relevant industry experience.
- Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related engineering field.
- In-depth understanding of CPU, GPU, Neural, and ML workloads and applications.
- Good understanding of control system applications and behavior.
- Expertise in high-performance SoC power delivery and thermals.
- Excellent modeling and simulator development skills.
- Ability to work with Claude to produce high-quality code with validation.
Responsibilities
- Drive development of Constrained Performance Model simulators.
- Collaborate with SoC, System, and Software Architects to influence the design of future Apple products.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
