Fellow, Platform Power Management Architect – AMD Instinct™ GPUs

Advanced Micro Devices, Inc•San Jose, CA

1d•Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role AMD is seeking a Platform Power Management Architect to define and drive end‑to‑end power architecture for AMD Instinct™ data center GPU platforms. This role is responsible for system‑level power strategy, spanning silicon capabilities, board‑level power delivery, firmware, Linux power management, and rack‑scale deployment considerations. The architect will work cross‑functionally with silicon, firmware, platform hardware, Linux kernel/ROCm software, and data center system teams to optimize performance per watt, ensure power integrity and reliability, and deliver accurate power projections for current and next‑generation Instinct platforms. Exposure to scale‑up or scale‑out networking fabrics is highly desirable.

Requirements

Expert-level background in platform, system, or silicon architecture with significant focus on power management.
Strong understanding of power delivery networks (PDN), voltage regulation, rail optimization, and power integrity fundamentals.
Hands‑on experience with Linux power management concepts, kernel/driver interactions, or system‑level power control.
Experience building or consuming power models and projections for complex systems.
Ability to work across hardware and software boundaries and influence architectural decisions.
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (Master’s or PhD preferred).

Nice To Haves

Experience with data center GPUs, accelerators, or high‑performance SoCs.
Exposure to scale‑up GPU fabrics and/or scale‑out data center networking.
Familiarity with telemetry, power capping, workload‑aware power management, or fleet‑level power optimization.
Experience presenting architectural trade‑offs to senior technical leadership.
Background in HPC or AI training/inference systems.

Responsibilities

Define the end‑to‑end power management architecture for AMD Instinct data center GPUs, spanning silicon, package, board, system, and rack levels.
Own platform‑level power concepts including power states, power limits, throttling policies, telemetry, and power‑performance trade‑offs.
Act as the technical authority for power‑related architectural decisions across multiple Instinct programs.
Lead power rail architecture and optimization, including rail partitioning, sequencing, voltage/frequency domains, and efficiency trade‑offs.
Partner with hardware and silicon teams to optimize VR efficiency, transient response, and steady‑state power delivery under AI/HPC workloads.
Influence silicon and platform features to improve power scalability and robustness across SKUs and deployment configurations.
Define requirements and architecture for Linux‑based power management, including interactions with kernel frameworks, drivers, firmware, and ROCm components.
Collaborate with software teams on power telemetry, control interfaces, policy enforcement, and observability.
Ensure alignment between platform power capabilities and software‑visible controls for data center operators.
Solid understanding of RTPM, ACPI and Suspend to Idle / S0ix flows.
Develop and own power projection methodologies for GPUs, platforms, and multi‑GPU systems across representative workloads.
Provide power projections and sensitivity analyses to support product planning, system design, customer engagements, and thermal/rack planning.
Validate projections against lab data and silicon characterization results, closing gaps between model and reality.
Incorporate scale‑up (e.g., high‑bandwidth GPU interconnects) and scale‑out (e.g., networking fabrics) considerations into platform power strategy.
Understand and influence the power impact of interconnects, NICs, switches, and fabric topologies in large GPU clusters.
Partner with fabric and system architects to ensure coherent power budgeting at node and rack scale.
Drive alignment across silicon, firmware, hardware, Linux, ROCm, platform, and data center solution teams.
Produce clear architectural documentation, power models, and executive‑level summaries.
Represent platform power architecture in technical reviews with senior leadership and external partners.