Platform Integration Engineer

Intel•Us, CA

2d•Hybrid

About The Position

The Central Engineering Group (CEG) at Intel drives innovation and excellence in silicon development by architecting, designing, and validating IP for Intel's technology portfolio. The position contributes to developing high-quality IP blocks and subsystems for integration into full-chip designs. Work includes creating logic designs, optimizing power, performance, area, and timing, and ensuring effective integration with the broader system. The work is intended to support next-generation silicon solutions with speed, efficiency, and reliability. The role is based in Santa Clara, California, and is eligible for Intel's hybrid work model, which allows time to be split between the assigned Intel site and off-site. The role is an experienced hire on Shift 1. Intel describes its total compensation package as including competitive pay, stock bonuses, and health, retirement, and vacation benefits. The posted annual salary range for US positions is $164,470 to $232,190, with individual pay depending on work location and factors including skills, experience, and education or training.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field and 6 or more years of experience with RTL design and SystemVerilog; alternatively, a relevant master's degree and 4 or more years of experience with RTL design and SystemVerilog.
Experience with industry-standard front-end design tools, including synthesis, static timing analysis (STA), and lint checks.
Experience with AMBA protocols and coherent protocols such as IDI or CHI.
Knowledge of hardware design concepts, including logic design, state machines, and network-on-chip architectures.
Ability to collaborate effectively across cross-functional and geographically distributed teams.
Strong attention to detail when reviewing verification plans and resolving design failures.
Passion for innovation and continuous improvement in a fast-paced engineering environment.

Nice To Haves

Experience with high-speed interconnect designs and power-performance optimization.
Proficiency in programming languages such as Python, Perl, or Tcl for scripting automation.
Demonstrated ability to collaborate effectively with cross-functional teams and geographically distributed groups.

Responsibilities

Develop logic designs, RTL code, and simulations for IP blocks and subsystems intended for integration into full-chip designs.
Define architecture and microarchitecture features and ensure their implementation in the design.
Optimize design logic to meet power, performance, area, and timing goals while maintaining physical implementation integrity.
Review verification plans and address RTL test failures to ensure accurate validation of design features.
Collaborate with physical design teams to address floorplan limitations and integrate designs seamlessly.
Drive quality assurance compliance to enable smooth IP-to-SoC handoff.