Physical design Staff Application engineer

Synopsys • Hillsboro, OR

8d • $112,000 - $168,000 • Onsite

About The Position

SYNOPSYS IS THE LEADER IN ENGINEERING SOLUTIONS FROM SILICON TO SYSTEMS, ENABLING CUSTOMERS TO RAPIDLY INNOVATE AI-POWERED PRODUCTS. WE DELIVER INDUSTRY-LEADING SILICON DESIGN, IP, SIMULATION AND ANALYSIS SOLUTIONS, AND DESIGN SERVICES. WE PARTNER CLOSELY WITH OUR CUSTOMERS ACROSS A WIDE RANGE OF INDUSTRIES TO MAXIMIZE THEIR R&D CAPABILITY AND PRODUCTIVITY, POWERING INNOVATION TODAY THAT IGNITES THE INGENUITY OF TOMORROW.

You have spent years in the trenches of physical design, working on chips that actually tape out and ship in products people use. The difference between a design that closes timing and one that burns three months of schedule is something you can see coming in the floorplan stage, and you are the kind of engineer who speaks up before it becomes a crisis. You know Fusion Compiler or ICC2 well enough that you can debug a routing congestion issue at 9pm on a customer call and walk out with a plan that actually works.

Scripting is not a side skill for you, it is how you think. You build flows in TCL and Python that do not just automate tasks but make design decisions smarter and more predictable. When someone says "the tool is doing something weird," you are the one who digs into the log files, finds the root cause, and writes the fix that prevents it from happening again.

You are comfortable working directly with customers, not just handing off a deck but sitting in the room, understanding their constraints, and building solutions that fit their reality. At Synopsys, you will work on the hardest physical design problems in the industry, on the most advanced nodes, with customers who are building the chips that power everything.

Requirements

• Bachelor's degree in electrical engineering or a related field with 5+ years of hands-on ASIC physical design experience, or a master's degree with 3+ years of experience
• Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus, you have used these tools on real tapeouts, not just in training
• Strong scripting and automation skills using TCL, Python, or Perl to build flows, analyze data, and solve problems that do not have a button in the GUI
• Solid understanding of advanced-node design challenges at 7nm and below, including FinFET effects, multi-patterning, electromigration, and the tradeoffs that come with each
• Experience with logical and physical synthesis flows, and familiarity with AI-driven optimization methodologies is a strong plus
• Excellent communication and presentation skills, you can explain a complex timing closure strategy to a customer engineering team and a high-level roadblock to their management in the same meeting
• Willingness to travel to customer sites as needed, sometimes on short notice, to provide onsite support during critical design phases

Nice To Haves

• You can walk into a customer meeting with incomplete information, ask the right questions, and leave with a clear plan that the team actually believes in
• When a design is failing timing by 500ps and the customer is two weeks from tape-out, you do not panic, you methodically work the problem until you find the path to closure
• You write scripts that other engineers can actually read and modify, not just code that works but code that scales across a team
• You push back when a methodology recommendation does not fit the customer's reality, even if it means more work to find the right answer
• You can explain a complex physical design tradeoff to a VP in two sentences without losing the nuance, and then turn around and debug a TCL flow issue with an engineer
• You treat customer problems like your own, not because you have to but because you care about the outcome and you know your work directly affects whether their chip succeeds or fails

Responsibilities

• Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Synopsys physical design tools including Fusion Compiler, helping them hit PPA targets under real schedule and resource constraints
• Develop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl to improve design quality, predictability, and team efficiency across the RTL-to-GDS flow
• Debug complex physical design challenges including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi-patterning and electromigration constraints
• Build and deliver methodology recommendations tailored to customer design constraints, process technologies, and project timelines, not generic best practices but solutions that fit their specific context
• Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve implementation challenges that traditional methods struggle with
• Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature enhancements that make it into the next release
• Travel to customer sites as needed to provide onsite support, training, and design reviews, often under tight deadlines and high-stakes tape-out pressure

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Monetary and non-monetary offerings
• Annual bonus
• Equity
• Other discretionary bonuses
• Comprehensive health, wellness, and financial benefits as part of a competitive total rewards package

What This Job Offers

• Job Type: Full-time
• Career Level: Senior