Physical Design Lead — Execution

Altera Semiconductor•San Jose, CA
•Onsite

About The Position

Altera is seeking a Physical Design Lead — Execution (Principal/Sr. Principal Engineer) to drive the day-to-day physical design execution and delivery of Altera's chips. This senior individual-contributor role is for an engineer who excels in block and full-chip closure, can take ownership of a design's execution, maintain schedules and quality under pressure, and act as a reliable resource for design teams during tight timelines. The role involves being the link between physical design blocks and full-chip integration, with potential for growth into owning full-chip implementation scope. Additionally, this position requires representing Altera's physical design execution to senior customers, necessitating comfort in technical discussions with customer leadership and resolving critical issues before tapeout. This role is part of Altera's senior individual-contributor (IC) technical ladder, designed for deep technical leaders who prefer to lead through expertise, execution, and influence rather than people management, while still shaping design delivery and mentoring junior engineers.

Requirements

  • Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
  • 15+ years (Sr. Principal Engineer) or 12+ years (Principal Engineer) of physical design experience.
  • A minimum of four full-chip tapeouts at advanced nodes with direct execution ownership.
  • A strong physical design execution track record, with direct accountability for schedule and quality outcomes across blocks and full chip.
  • Demonstrated ability to deliver under schedule pressure without compromising quality, including experience managing critical-path recovery.
  • Hands-on expertise across the physical design flow — floorplanning, placement, clock-tree synthesis, routing, and timing/power closure — and how these interact with signoff.
  • Production physical design execution experience at advanced nodes (e.g., 7nm / 5nm / 3nm / Intel 18A) or comparable, including specific parasitic and reliability challenges.
  • Hands-on proficiency with industry-standard implementation and signoff tools — Synopsys Fusion Compiler / ICC2 / PrimeTime, Cadence Innovus / Tempus / Voltus, Ansys RedHawk-SC, Siemens Calibre, or equivalent.
  • Working command of the horizontal signoff flows that gate tapeout: timing closure (STA), EMIR, physical verification, formal equivalence, and low-power verification.
  • Scripting and automation proficiency (Python, Tcl, Perl, or shell) sufficient to build and debug execution tooling.
  • Experience driving execution on designs of high complexity with concurrent block teams across multiple sites.
  • Demonstrated ability to engage senior customers, build rapport, and navigate challenging technical conversations with credibility, diplomacy, and influence.
  • Strong organizational and cross-team coordination skills, with a track record of resolving conflicting priorities across design teams.
  • Excellent communication skills, equally comfortable presenting to engineering teams and to senior stakeholders, internal and external.

Nice To Haves

  • Experience serving as an implementation lead or execution owner for a full chip or major subsystem.
  • Direct experience representing physical design execution in customer-facing technical reviews.
  • Working familiarity with PD signoff methodology (EMIR, timing, power) sufficient to partner effectively with methodology teams.
  • Experience mentoring or informally leading execution teams without formal management authority.

Responsibilities

  • Drive day-to-day physical design execution and delivery across blocks and full-chip integration, from floorplan through tapeout.
  • Own the schedule and quality bar for physical design execution, proactively identifying risk and driving mitigation before it threatens a milestone.
  • Coordinate execution across multiple blocks and design teams, resolving conflicts and dependencies to keep full-chip closure on track.
  • Grow into ownership of full-chip implementation scope, building the technical judgment and organizational relationships required for that role.
  • Engage senior customer technical stakeholders directly, building rapport and navigating challenging technical conversations with credibility, diplomacy, and influence.
  • Serve as the escalation point for execution blockers, driving fast, pragmatic resolution under schedule pressure.
  • Partner with methodology and CAD teams to ensure execution practices align with signoff standards and quality gates.
  • Mentor physical design engineers on execution best practices, prioritization, and schedule management.

Benefits

  • Incentive opportunities that reward employees based on individual and company performance.
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