Physical Design Lead — Execution

Altera•San Jose, CA

8d•$231,500 - $341,075•Onsite

About The Position

Altera builds the programmable logic and adaptive computing solutions that power the world's most demanding systems — from data centers and networking infrastructure to automotive, aerospace, and industrial applications. As an independent FPGA leader, we combine decades of silicon expertise with a startup's focus on speed and innovation. Our engineers work at the edge of process technology and design methodology to deliver silicon that customers can trust, on schedule, every time. We are looking for a Physical Design Lead — Execution (Principal/Sr. Principal Engineer) to drive the day-to-day physical design execution and delivery that gets Altera's chips across the finish line. This is a senior individual-contributor role for an engineer who thrives in the trenches of block and full-chip closure — someone who can take ownership of a design's execution, hold the schedule and quality bar under pressure, and be the steady hand design teams turn to when timelines get tight. You will be the connective tissue between physical design blocks and full-chip integration, with a clear growth path toward owning full-chip implementation scope. Because this role also represents Altera's physical design execution in front of senior customers, you'll need to be just as comfortable in a candid technical conversation with a customer's technical leadership as you are resolving a critical-path issue days before tapeout. This role sits on Altera's senior individual-contributor (IC) technical ladder. It is built for deep technical leaders who prefer to lead through expertise, execution, and influence rather than people management — while still shaping how design teams deliver and mentoring the next generation of physical design engineers.

Requirements

Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, plus 15+ years (Sr. Principal Engineer) or 12+ years (Principal Engineer) of physical design experience, including a minimum of four full-chip tapeouts at advanced nodes with direct execution ownership.
A strong physical design execution track record, with direct accountability for schedule and quality outcomes across blocks and full chip.
Demonstrated ability to deliver under schedule pressure without compromising quality, including experience managing critical-path recovery.
Hands-on expertise across the physical design flow — floorplanning, placement, clock-tree synthesis, routing, and timing/power closure — and how these interact with signoff.
Hands-on proficiency with industry-standard implementation and signoff tools — Synopsys Fusion Compiler / ICC2 / PrimeTime, Cadence Innovus / Tempus / Voltus, Ansys RedHawk-SC, Siemens Calibre, or equivalent. Experience with every tool is not required.
Working command of the horizontal signoff flows that gate tapeout: timing closure (STA), EMIR, physical verification, formal equivalence, and low-power verification.
Scripting and automation proficiency (Python, Tcl, Perl, or shell) sufficient to build and debug execution tooling, not only to run it.
Experience driving execution on designs of high complexity with concurrent block teams across multiple sites.
Demonstrated ability to engage senior customers, build rapport, and navigate challenging technical conversations with credibility, diplomacy, and influence.
Strong organizational and cross-team coordination skills, with a track record of resolving conflicting priorities across design teams.
Excellent communication skills, equally comfortable presenting to engineering teams and to senior stakeholders, internal and external.

Nice To Haves

Experience serving as an implementation lead or execution owner for a full chip or major subsystem.
Direct experience representing physical design execution in customer-facing technical reviews.
Working familiarity with PD signoff methodology (EMIR, timing, power) sufficient to partner effectively with methodology teams.
Experience mentoring or informally leading execution teams without formal management authority.

Responsibilities

Execution ownership — Drive day-to-day physical design execution and delivery across blocks and full-chip integration, from floorplan through tapeout.
Schedule & quality — Own the schedule and quality bar for physical design execution, proactively identifying risk and driving mitigation before it threatens a milestone.
Cross-block coordination — Coordinate execution across multiple blocks and design teams, resolving conflicts and dependencies so full-chip closure stays on track.
Scope growth — Grow into ownership of full-chip implementation scope, building the technical judgment and organizational relationships that role demands.
Customer engagement — Engage senior customer technical stakeholders directly, building rapport and navigating challenging technical conversations with credibility, diplomacy, and influence.
Escalation & problem-solving — Serve as the escalation point for execution blockers, driving fast, pragmatic resolution under schedule pressure.
Process discipline — Partner with methodology and CAD teams to ensure execution practices stay aligned with signoff standards and quality gates.
Mentorship — Mentor physical design engineers on execution best practices, prioritization, and schedule management.