Physical Design Engineer

Apple•Cupertino, CA

17d•$150,400 - $225,300•Hybrid

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. DESCRIPTION APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Collaborate with the package and floorplan teams on pad ring, bump, and RDL designs; Perform various types of physical verification checks (LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level; Interface with the CAD/Technology teams for flow bring up and validation; Collaborate with the implementation team during the entire chip design cycle to drive signoff closure for tape out; Support schedules and cross-functional engineering effort; Work with FE team to understand chip architecture and drive physical verification aspects early in design cycle. Configure, review, and provide timely feedback on full chip DRC, LVS, PERC and other full chip physical verification analysis; Work with physical design team, drive methodologies and "best known methods" to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress while offering physical verification support; Support partition owners with PnR activities, set goals, plan short and long-term work, understand dependencies between different domains like top, STA, block PnR; and Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. 40 hours/week.

Requirements

DRC debug--Review custom, analog, and digital physical design data using industry standard Design Rule Checking, e.g. Calibre DRC and provide guidance to design owners to resolve all violations.
LVS debug--Review custom, analog, and digital physical design data using industry standard Layout Versus Schematic checks, e.g. Calibre LVS and provide guidance to design owners to resolve all mismatches.
CMOS Layout Design--Design custom layout and routing to be used in product and test chips using industry standard tools, e.g. Cadence Virtuoso, including but not limited to bumps and RDL.
PNR/APR implementation--Design auto Place And Route designs using industry standard PNR tools, e.g. Cadence Innovus.
Tcl/Perl/Python script development--specify and code Tcl/Perl/Python scripts to facilitate the design, verification, and signoff of physical design data.

Responsibilities

Collaborate with the package and floorplan teams on pad ring, bump, and RDL designs
Perform various types of physical verification checks (LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level
Interface with the CAD/Technology teams for flow bring up and validation
Collaborate with the implementation team during the entire chip design cycle to drive signoff closure for tape out
Support schedules and cross-functional engineering effort
Work with FE team to understand chip architecture and drive physical verification aspects early in design cycle
Configure, review, and provide timely feedback on full chip DRC, LVS, PERC and other full chip physical verification analysis
Work with physical design team, drive methodologies and "best known methods" to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress while offering physical verification support
Support partition owners with PnR activities, set goals, plan short and long-term work, understand dependencies between different domains like top, STA, block PnR
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution