Physical Design Engineer

Apple•Austin, TX

6d•Onsite

About The Position

Perform physical design implementation of SOC (system-on-ship) blocks. Collaborate with other teams to ensure the block integrates without issues, into the next level of the design hierarchy. Collaborate with the FE team to understand chip architecture and drive physical aspects early in the design cycle. Drive methodologies and best-known methods to streamline physical design work, come up with guidelines and checklists, and track progress. Resolve design and flow issues related to physical design, identify potential solutions and drive execution. Analyze reports, query the design database for proper structure, identify issues, and write scripts using the native tool commands to develop solutions. Carry out the physical implementation of one or more complex System-On-Chip (SOC) blocks from netlist to tape-out in advanced technology nodes. Improve the current implementation methodology, tuning flows, and construction recipes to improve the power, performance, and area of implemented blocks. Collaborate with the RTL design team to understand the logic and data flow of the block, perform placement of memories and other macros in the design, implement clock and power distribution, and placement and routing of the entire block. Optimize the design for reduced area and power and timing convergence, including understanding the clock architecture to optimize clock distribution, resolving congestion hotspots, adding placement and grouping constraints, implementing custom routing solutions and other techniques to optimize the design. Perform various analysis tasks on the block such as Static timing analysis (STA), Voltage drop analysis static (IR)/ dynamic internal voltage deviation (IVD), Design Rule Checking (DRC)/ Layout vs. Schematic (LVS), and clean up violations to provide a clean database. Interact with top-level integration, timing, and electrical analysis teams. Participate in improving block construction recipes for a certain technology and/or tool set. Create methodology changes to improve the quality or turn-around time of implementation. Analyze collected data and utilize scripting techniques to extract trends and meaningful conclusions.

Requirements

Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field and 5 years of experience in the job offered or related occupation.
Utilizing Electronic Design Automation (EDA) tools such as Innovus or IC Compiler, Primetime or Calibre.
Experience in synthesis, automated place and route, or verification flows, including logic equivalency, low power verification, or physical design verification.
Understanding and interpreting design constraints for timing convergence and low power verification.
Utilizing circuit design techniques like clock gating, power gating, or multi-voltage designs to optimize power performance and minimize area tradeoffs.
Using hardware descriptive languages to accurately describe the behavior and structure of digital circuits.
Automating repetitive processes, data and text processing, and complex data analysis using scripting languages such as Perl, Shell scripting, Makefiles, and TCL.
Performing block and IP level floorplanning tasks such as pin assignment and Macro Placement.
Performing routing and congestion analysis.

Responsibilities

Perform physical design implementation of SOC (system-on-chip) blocks.
Collaborate with other teams to ensure the block integrates without issues, into the next level of the design hierarchy.
Collaborate with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
Drive methodologies and best-known methods to streamline physical design work, come up with guidelines and checklists, and track progress.
Resolve design and flow issues related to physical design, identify potential solutions and drive execution.
Analyze reports, query the design database for proper structure, identify issues, and write scripts using the native tool commands to develop solutions.
Carry out the physical implementation of one or more complex System-On-Chip (SOC) blocks from netlist to tape-out in advanced technology nodes.
Improve the current implementation methodology, tuning flows, and construction recipes to improve the power, performance, and area of implemented blocks.
Collaborate with the RTL design team to understand the logic and data flow of the block, perform placement of memories and other macros in the design, implement clock and power distribution, and placement and routing of the entire block.
Optimize the design for reduced area and power and timing convergence, including understanding the clock architecture to optimize clock distribution, resolving congestion hotspots, adding placement and grouping constraints, implementing custom routing solutions and other techniques to optimize the design.
Perform various analysis tasks on the block such as Static timing analysis (STA), Voltage drop analysis static (IR)/ dynamic internal voltage deviation (IVD), Design Rule Checking (DRC)/ Layout vs. Schematic (LVS), and clean up violations to provide a clean database.
Interact with top-level integration, timing, and electrical analysis teams.
Participate in improving block construction recipes for a certain technology and/or tool set.
Create methodology changes to improve the quality or turn-around time of implementation.
Analyze collected data and utilize scripting techniques to extract trends and meaningful conclusions.