Physical Design Engineer

Apple•Austin, TX

18d•Onsite

About The Position

Collaborate with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs; Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle; Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals; Time, physical and electrical verification, and driving the signoff closure for the partitions; Resolve and improving design and flow issues related to physical design, identifying potential solutions, and driving execution; Work with logic designer to decide on design hierarchy and to architect macro/design module placement to extract best PPA at floorplan stage; Work with EDA tools to optimize the design to get best placement location for millions of cells in the design; Construct clock tree to support high performance and low power designs; Route the design to meet all latest technology foundry guidelines and rules; Verify design performance using Static analysis, generating ECOs to fix failing paths; Verify design for electrical rules checks, designing rule checks, electromigration and IR drop. Fix any of the violations on physical database; Review and signoff the design to make sure quality and PPA is not compromised; Identifying issue, debugging, resolving flow issues during place and route implementation; Develop scripts/programs as needed to implement and signoff designs; Understand weekly handoff requirements and run flows to delivered required data; and Work with IP leads to understand design violations and deliver fixes.

Requirements

Bachelor’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering or a related field
Utilizing experience using industry standard tools for PnR to implement and signoff off SOC design partitions
Utilizing industry stand timing tools to perform STA across multiple corners and modes, fixing setup and hold violations and debugging timing paths
Creating a block-level floorplan including macro placement, pin assignment, power grid design, tap cell insertion, and congestion reduction
Run and debug DRC and LVS using tools to complete PV signoff and ensure design meets foundry DRM specs
Generating and analyzing clock trees, reducing skew and jitter, and optimizing buffer insertion
Performing manual and tool-driven ECOs for timing (buffer insertion, cell sizing) for final STA signoff and closure of design
Utilizing skills in power (leakage recovery, Vt swaps) and functional changes (gate-level patching)
Utilizing skills in TCL and Shell Scripting to automate PnR flows, parse reports, or create CAD utilities

Responsibilities

Collaborate with architecture, CAD, timing and logic design teams
Understand partition architecture and drive physical aspects early in the design cycle
Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals
Perform time, physical and electrical verification, and drive signoff closure for partitions
Resolve and improve design and flow issues related to physical design
Architect macro/design module placement to extract best PPA at floorplan stage
Optimize the design using EDA tools for placement
Construct clock tree for high performance and low power designs
Route the design to meet technology foundry guidelines and rules
Verify design performance using Static analysis and generate ECOs to fix failing paths
Verify design for electrical rules checks, designing rule checks, electromigration and IR drop
Fix violations on physical database
Review and signoff the design
Identify issues, debug, and resolve flow issues during place and route implementation
Develop scripts/programs to implement and signoff designs
Understand weekly handoff requirements and run flows to deliver required data
Work with IP leads to understand design violations and deliver fixes