Physical Design Engineer, PnR

Tenstorrent•Fort Collins, CO

1d•Hybrid

About The Position

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Requirements

Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II.
Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability.
UPF/multi-voltage power domains
SoC interface IP integration (e.g. I3C, UART)
Signoff breadth (DRC/LVS, EM/IR, LEC/Formality)
Multi-clock/CDC-aware implementation
PLL/DLL integration
DFT-aware physical implementation (OCC/MBIST)

Responsibilities

Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC.
Help close EM/IR, ensure UPF power intent is consistent with implementation, and drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.