Physical Design Engineer I (Co-op) - United States

Cisco•Maynard, MA

2d•$44,000 - $185,000•Remote

About The Position

This posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Meet the Team Cisco is well known for developing ground-breaking products in short time intervals. To support new product development at an exciting pace the Acacia PD team is challenged to design, develop, and build ASIC designs. The work is essential for supporting the increasing demands of hybrid work environments and ensuring reliable, high-capacity network connections. The engineers work with technologies that involve the latest submicron technologies. An ASIC PD engineer would be involved in developing and optimizing physical floorplan and their implementation. Your Impact You'll perform one or more of the following tasks while working on Cisco's elite optical communication products. You'll be assigned relevant work assignments to challenge you according to your current level of experience and capability. You may find yourself working in the following areas: Work with Front-End teams to understand the design architecture to ensure optimal physical implementation Gate level netlist synthesis (physical synthesis) Physical implementation (floorplanning, placement, CTS, routing) Power, performance and area optimization of design Static Timing analysis and signoff closure Physical verification and signoff closure EMIR analysis and signoff closure

Requirements

Currently enrolled in an undergraduate degree program (Associate's or Bachelor's)
Qualifying education should be in Computer Science, Electrical Engineering, or related program
Expected to continue enrollment in degree program following completion of the internship.
Knowledge of the design cycle from RTL to GDSII
Understanding of Static Timing Analysis, timing closure and design constraints
Knowledge in block level synthesis, place and route, timing closure, PnR and signoff tools and their capabilities

Nice To Haves

Interest in VLSI design, and more specifically in ASIC physical design and verification
Interest and preferably academic experience in deep submicron CMOS technologies
Scripting experience with perl, tcl, python and/or shell, a plus
Analytical and creative, with well-developed and tenacious problem-solving skills
Previous internship experience

Responsibilities

Work with Front-End teams to understand the design architecture to ensure optimal physical implementation
Gate level netlist synthesis (physical synthesis)
Physical implementation (floorplanning, placement, CTS, routing)
Power, performance and area optimization of design
Static Timing analysis and signoff closure
Physical verification and signoff closure
EMIR analysis and signoff closure

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
flexible vacation time off program
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses
performance-based incentive pay